diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 1decdf97ca..11e8c985c1 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -41,6 +41,8 @@ CortexA76::initState()
 {
     for (auto *tc : threadContexts)
         tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, params().cntfrq);
+
+    evs_base_cpu->setSysCounterFrq(cluster->params().cntfrq);
 }
 
 void
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 29d8877f67..02ccaaba3d 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -44,6 +44,13 @@ ScxEvsCortexA76<Types>::setClkPeriod(Tick clk_period)
     clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
 }
 
+template <class Types>
+void
+ScxEvsCortexA76<Types>::setSysCounterFrq(uint64_t sys_counter_frq)
+{
+    periphClockRateControl->set_mul_div(sys_counter_frq, 1);
+}
+
 template <class Types>
 void
 ScxEvsCortexA76<Types>::setCluster(SimObject *cluster)
@@ -86,6 +93,7 @@ ScxEvsCortexA76<Types>::ScxEvsCortexA76(
     }
 
     clockRateControl.bind(this->clock_rate_s);
+    periphClockRateControl.bind(this->periph_clock_rate_s);
 }
 
 template <class Types>
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh b/src/arch/arm/fastmodel/CortexA76/evs.hh
index fa12ff8217..4aa43b6b25 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -63,6 +63,7 @@ class ScxEvsCortexA76 : public Types::Base, public Iris::BaseCpuEvs
     SC_HAS_PROCESS(ScxEvsCortexA76);
 
     ClockRateControlInitiatorSocket clockRateControl;
+    ClockRateControlInitiatorSocket periphClockRateControl;
 
     typedef sc_gem5::TlmTargetBaseWrapper<
         64, svp_gicv3_comms::gicv3_comms_fw_if,
@@ -105,6 +106,8 @@ class ScxEvsCortexA76 : public Types::Base, public Iris::BaseCpuEvs
 
     void setClkPeriod(Tick clk_period) override;
 
+    void setSysCounterFrq(uint64_t sys_counter_frq) override;
+
     void setCluster(SimObject *cluster) override;
 };
 
diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
index 1968931bec..04dae41310 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -35,7 +35,7 @@ component CortexA76x1
         // Clocks.
         clock1Hz : MasterClock();
         clockDiv : ClockDivider();
-        clockDivPeriph : ClockDivider(mul=0x01800000);
+        clockDivPeriph : ClockDivider();
     }
 
     connection
@@ -77,6 +77,13 @@ component CortexA76x1
             clockDiv.rate.set64(mul, div);
         }
     }
+    slave port<ExportedClockRateControl> periph_clock_rate_s
+    {
+        behavior set_mul_div(uint64_t mul, uint64_t div)
+        {
+            clockDivPeriph.rate.set64(mul, div);
+        }
+    }
     slave port<GICv3Comms> redistributor[1];
 
     // External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
index e0f7a93303..0279140552 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
@@ -35,7 +35,7 @@ component CortexA76x2
         // Clocks.
         clock1Hz : MasterClock();
         clockDiv : ClockDivider();
-        clockDivPeriph : ClockDivider(mul=0x01800000);
+        clockDivPeriph : ClockDivider();
     }
 
     connection
@@ -77,6 +77,13 @@ component CortexA76x2
             clockDiv.rate.set64(mul, div);
         }
     }
+    slave port<ExportedClockRateControl> periph_clock_rate_s
+    {
+        behavior set_mul_div(uint64_t mul, uint64_t div)
+        {
+            clockDivPeriph.rate.set64(mul, div);
+        }
+    }
     slave port<GICv3Comms> redistributor[2];
 
     // External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
index 9ce9027e45..b18b10239c 100644
--- a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
@@ -35,7 +35,7 @@ component CortexA76x3
         // Clocks.
         clock1Hz : MasterClock();
         clockDiv : ClockDivider();
-        clockDivPeriph : ClockDivider(mul=0x01800000);
+        clockDivPeriph : ClockDivider();
     }
 
     connection
@@ -77,6 +77,13 @@ component CortexA76x3
             clockDiv.rate.set64(mul, div);
         }
     }
+    slave port<ExportedClockRateControl> periph_clock_rate_s
+    {
+        behavior set_mul_div(uint64_t mul, uint64_t div)
+        {
+            clockDivPeriph.rate.set64(mul, div);
+        }
+    }
     slave port<GICv3Comms> redistributor[3];
 
     // External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
index e4b79ce1b3..c7f1cb2ecd 100644
--- a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
@@ -35,7 +35,7 @@ component CortexA76x4
         // Clocks.
         clock1Hz : MasterClock();
         clockDiv : ClockDivider();
-        clockDivPeriph : ClockDivider(mul=0x01800000);
+        clockDivPeriph : ClockDivider();
     }
 
     connection
@@ -77,6 +77,13 @@ component CortexA76x4
             clockDiv.rate.set64(mul, div);
         }
     }
+    slave port<ExportedClockRateControl> periph_clock_rate_s
+    {
+        behavior set_mul_div(uint64_t mul, uint64_t div)
+        {
+            clockDivPeriph.rate.set64(mul, div);
+        }
+    }
     slave port<GICv3Comms> redistributor[4];
 
     // External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc b/src/arch/arm/fastmodel/CortexR52/evs.cc
index cd84aa62e7..f4ce61e308 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -43,6 +43,13 @@ ScxEvsCortexR52<Types>::setClkPeriod(Tick clk_period)
     clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
 }
 
+template <class Types>
+void
+ScxEvsCortexR52<Types>::setSysCounterFrq(uint64_t sys_counter_frq)
+{
+    panic("Not implemented for R52.");
+}
+
 template <class Types>
 void
 ScxEvsCortexR52<Types>::setCluster(SimObject *cluster)
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh b/src/arch/arm/fastmodel/CortexR52/evs.hh
index e03a32200b..3fa5980a84 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -140,6 +140,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
 
     void setClkPeriod(Tick clk_period) override;
 
+    void setSysCounterFrq(uint64_t sys_counter_frq) override;
+
     void setCluster(SimObject *cluster) override;
 };
 
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index c5dd19f243..369f0d8da8 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -44,6 +44,7 @@ class BaseCpuEvs
   public:
     virtual void sendFunc(PacketPtr pkt) = 0;
     virtual void setClkPeriod(Tick clk_period) = 0;
+    virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
     virtual void setCluster(SimObject *cluster) = 0;
 };