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arch-arm: Remove SPSR write mask

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We are currently masking out the PAN and UAO field when writing
to the SPSR_ELx register.
This is not needed and we should treat them as RES0 instead if
FEAT_PAN and FEAT_UAO are not implemented

Change-Id: Ib65e3744f365825d2414b8092b3a79324be461b4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50389
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2021-09-01 15:30:07 +01:00
parent cbffe30e64
commit ee0e92a432
1 changed files with 0 additions and 10 deletions
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10
src/arch/arm/isa.cc
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@@ -2316,16 +2316,6 @@ ISA::setMiscReg(int misc_reg, RegVal val)
case MISCREG_AT_S1E3W_Xt:
addressTranslation64(MMU::S1E3Tran, BaseMMU::Write, 0, val);
return;
case MISCREG_SPSR_EL3:
case MISCREG_SPSR_EL2:
case MISCREG_SPSR_EL1:
{
RegVal spsr_mask = havePAN ?
~(0x2 << 22) : ~(0x3 << 22);
newVal = val & spsr_mask;
break;
}
case MISCREG_L2CTLR:
warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
miscRegName[misc_reg], uint32_t(val));