From ee0e92a432acc21ab03ec250d7328c2f9ec6e916 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 1 Sep 2021 15:30:07 +0100 Subject: [PATCH] arch-arm: Remove SPSR write mask We are currently masking out the PAN and UAO field when writing to the SPSR_ELx register. This is not needed and we should treat them as RES0 instead if FEAT_PAN and FEAT_UAO are not implemented Change-Id: Ib65e3744f365825d2414b8092b3a79324be461b4 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50389 Tested-by: kokoro Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/isa.cc | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 9439d0eba5..9caf5f777f 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -2316,16 +2316,6 @@ ISA::setMiscReg(int misc_reg, RegVal val) case MISCREG_AT_S1E3W_Xt: addressTranslation64(MMU::S1E3Tran, BaseMMU::Write, 0, val); return; - case MISCREG_SPSR_EL3: - case MISCREG_SPSR_EL2: - case MISCREG_SPSR_EL1: - { - RegVal spsr_mask = havePAN ? - ~(0x2 << 22) : ~(0x3 << 22); - - newVal = val & spsr_mask; - break; - } case MISCREG_L2CTLR: warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", miscRegName[misc_reg], uint32_t(val));