arch-arm: Revert 'Setup TC/ISA at construction time..'

Reverts:

dd2f1fb2f8
https://gem5-review.googlesource.com/c/public/gem5/+/65174

and

47bd56ee71
https://gem5-review.googlesource.com/c/public/gem5/+/65291

The 47bd56ee change resulted in the
`SuiteUID:tests/gem5/fs/linux/arm/test.py:realview-switcheroo-noncaching-timing-ALL-x86_64-opt`
nightly test stalling. This behavior can be reproduced with:

```
./build/ALL/gem5.opt tests/gem5/fs/linux/arm/run.py tests/gem5/configs/realview-switcheroo-noncaching-timing.py tests/gem5/resources/arm “$(pwd)”
```

The subsequent change, dd2f1fb2, must be reverted for this change to be
reverted.

Change-Id: I6fed74f33d013f321b93cf1a73eee404cb87ce18
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65732
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/isa.cc

@@ -523,6 +523,16 @@ ISA::setupThreadContext()
         return;
 
     selfDebug->init(tc);
+
+    Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
+    if (!gicv3)
+        return;
+
+    if (!gicv3CpuInterface)
+        gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+
+    gicv3CpuInterface->setISA(this);
+    gicv3CpuInterface->setThreadContext(tc);
 }
 
 void
@@ -1998,15 +2008,7 @@ ISA::getGenericTimer()
 BaseISADevice &
 ISA::getGICv3CPUInterface()
 {
-    if (gicv3CpuInterface)
-        return *gicv3CpuInterface.get();
-
-    assert(system);
-    Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
-    panic_if(!gicv3, "The system does not have a GICv3 irq controller\n");
-
-    gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-
+    panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
     return *gicv3CpuInterface.get();
 }