arch-riscv: This commit fixes bug in vfmv.f.s impl. in riscv (#863)

The existing implementation of vfmv instruction did not type cast the
first element of the source vector, which caused the "freg" to interpret
the result as a NaN.

With the type cast to f32, the value is correctly recognized as float
and sign extended to be stored in the fd register.

Git issue: https://github.com/gem5/gem5/issues/827

Change-Id: Ibe9873910827594c0ec11cb51ac0438428c3b54e

---------

Co-authored-by: Debjyoti B <bhatta53@imec.be>
Co-authored-by: Tommaso Marinelli <tommarin@ucm.es>

src/arch/riscv/isa/decoder.isa

@@ -3086,7 +3086,7 @@ decode QUADRANT default Unknown::unknown() {
                         // The encodings corresponding to the masked versions
                         // (vm=0) of vfmv.f.s are reserved
                         0x1: VectorNonSplitFormat::vfmv_f_s({{
-                            freg_t fd = freg(Vs2_vu[0]);
+                            freg_t fd = freg(ftype<et>(Vs2_vu[0]));
                             Fd_bits = fd.v;
                         }}, OPFVV, VectorMiscOp);
                     }