From ec690de0da53d9604cc24cb9384ea66b10228cb3 Mon Sep 17 00:00:00 2001 From: Debjyoti Bhattacharjee Date: Fri, 29 Mar 2024 16:23:14 +0100 Subject: [PATCH] arch-riscv: This commit fixes bug in vfmv.f.s impl. in riscv (#863) The existing implementation of vfmv instruction did not type cast the first element of the source vector, which caused the "freg" to interpret the result as a NaN. With the type cast to f32, the value is correctly recognized as float and sign extended to be stored in the fd register. Git issue: https://github.com/gem5/gem5/issues/827 Change-Id: Ibe9873910827594c0ec11cb51ac0438428c3b54e --------- Co-authored-by: Debjyoti B Co-authored-by: Tommaso Marinelli --- src/arch/riscv/isa/decoder.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 2147d8701b..995b4936b5 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -3086,7 +3086,7 @@ decode QUADRANT default Unknown::unknown() { // The encodings corresponding to the masked versions // (vm=0) of vfmv.f.s are reserved 0x1: VectorNonSplitFormat::vfmv_f_s({{ - freg_t fd = freg(Vs2_vu[0]); + freg_t fd = freg(ftype(Vs2_vu[0])); Fd_bits = fd.v; }}, OPFVV, VectorMiscOp); }