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cpu: Set up _*_ports values in BaseCPU in __init__.

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This means that if ArchMMU came from the CPU class itself, subclasses
would have a chance to define their own version before the BaseCPU
method consumed it.

The intention is that Arch* *will* be defined in subclasses in later
changes, which will make this more important.

Change-Id: Ib20d5b10aeb26d33840cca4b5a1085d9c73f10de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52489
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-29 01:07:06 -07:00
parent 3f5cab5a9d
commit e60fcfe004
1 changed files with 16 additions and 6 deletions
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22
src/cpu/BaseCPU.py
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@@ -172,14 +172,8 @@ class BaseCPU(ClockedObject):
dcache_port = RequestPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
_cached_ports += ArchMMU.walkerPorts()
_uncached_interrupt_response_ports = []
_uncached_interrupt_request_ports = []
if buildEnv['TARGET_ISA'] == 'x86':
_uncached_interrupt_response_ports += ["interrupts[0].pio",
"interrupts[0].int_responder"]
_uncached_interrupt_request_ports += ["interrupts[0].int_requestor"]
def createInterruptController(self):
self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
@@ -303,3 +297,19 @@ class BaseCPU(ClockedObject):
def __init__(self, **kwargs):
super().__init__(**kwargs)
self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']
self._cached_ports = self._cached_ports + ArchMMU.walkerPorts()
# Practically speaking, these ports will exist on the x86 interrupt
# controller class.
if "pio" in ArchInterrupts._ports:
self._uncached_interrupt_response_ports = \
self._uncached_interrupt_response_ports + ["interrupts[0].pio"]
if "int_responder" in ArchInterrupts._ports:
self._uncached_interrupt_response_ports = \
self._uncached_interrupt_response_ports + [
"interrupts[0].int_responder"]
if "int_requestor" in ArchInterrupts._ports:
self._uncached_interrupt_request_ports = \
self._uncached_interrupt_request_ports + [
"interrupts[0].int_requestor"]