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cpu: Remove an architecture check in addPrivateSplitL1Caches.

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If there are iwc and dwc parameters, then they need to be hooked up. If
not, then they don't. There's no need to check the ISA as well.

Change-Id: I98cb831ab6d3f829ccab80e128105245e434a35c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52488
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-29 01:45:41 -07:00
parent 6dc5cfe34b
commit 3f5cab5a9d
1 changed files with 14 additions and 15 deletions
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29
src/cpu/BaseCPU.py
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@@ -208,22 +208,21 @@ class BaseCPU(ClockedObject):
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
self.mmu.connectWalkerPorts(
iwc.cpu_side, dwc.cpu_side)
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
else:
self._cached_ports += ArchMMU.walkerPorts()
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
self.mmu.connectWalkerPorts(
iwc.cpu_side, dwc.cpu_side)
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
else:
self._cached_ports += ArchMMU.walkerPorts()
# Checker doesn't need its own tlb caches because it does
# functional accesses only
if self.checker != NULL:
self._cached_ports += [ "checker." + port
for port in ArchMMU.walkerPorts() ]
# Checker doesn't need its own tlb caches because it does
# functional accesses only
if self.checker != NULL:
self._cached_ports += [ "checker." + port
for port in ArchMMU.walkerPorts() ]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,
xbar=None):