fastmodel: Create a fake "Interrupts" object for fast model CPUs.

This object doesn't actually manage interrupts since the fast model
CPUs do that on their own, it just checkpoints interrupt related state.

Change-Id: I9d3a6354b02e4ae7bfd032c50e51a3a841b81388
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29821
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py

@@ -43,7 +43,6 @@ class FastModelCortexA76(IrisBaseCPU):
     cntfrq = Param.UInt64(0x1800000, "Value for the CNTFRQ timer register")
 
     # We shouldn't need these, but gem5 gets mad without them.
-    interrupts = [ ArmInterrupts() ]
     isa = [ ArmISA() ]
 
     evs = Parent.evs

src/arch/arm/fastmodel/CortexA76/thread_context.cc

@@ -231,7 +231,7 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({
         // ArmISA::MISCREG_NMRR_MAIR1_S?
         // ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR?
         // ArmISA::MISCREG_SCTLR_RST?
-        // ArmISA::MISCREG_SEV_MAILBOX?
+        { ArmISA::MISCREG_SEV_MAILBOX, "SEV_STATE" },
 
         // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
         // ArmISA::MISCREG_DBGDIDR?

src/arch/arm/fastmodel/iris/Iris.py

@@ -27,6 +27,7 @@ from m5.params import *
 from m5.proxy import *
 
 from m5.objects.BaseCPU import BaseCPU
+from m5.objects.BaseInterrupts import BaseInterrupts
 from m5.objects.BaseTLB import BaseTLB
 
 class IrisTLB(BaseTLB):
@@ -34,6 +35,11 @@ class IrisTLB(BaseTLB):
     cxx_class = 'Iris::TLB'
     cxx_header = 'arch/arm/fastmodel/iris/tlb.hh'
 
+class IrisInterrupts(BaseInterrupts):
+    type = 'IrisInterrupts'
+    cxx_class = 'Iris::Interrupts'
+    cxx_header = 'arch/arm/fastmodel/iris/interrupts.hh'
+
 class IrisBaseCPU(BaseCPU):
     type = 'IrisBaseCPU'
     abstract = True
@@ -60,3 +66,6 @@ class IrisBaseCPU(BaseCPU):
 
     dtb = IrisTLB()
     itb = IrisTLB()
+
+    def createInterruptController(self):
+        self.interrupts = [ IrisInterrupts() for i in range(self.numThreads) ]

src/arch/arm/fastmodel/iris/SConscript

@@ -30,6 +30,7 @@ if not env['USE_ARM_FASTMODEL']:
 
 SimObject('Iris.py')
 Source('cpu.cc')
+Source('interrupts.cc')
 Source('tlb.cc')
 
 Source('thread_context.cc')

src/arch/arm/fastmodel/iris/interrupts.cc

@@ -0,0 +1,114 @@
+/*
+ * Copyright 2019 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/arm/fastmodel/iris/interrupts.hh"
+
+#include "arch/arm/fastmodel/iris/thread_context.hh"
+#include "arch/arm/isa_traits.hh"
+#include "arch/arm/miscregs.hh"
+#include "arch/arm/miscregs_types.hh"
+#include "arch/arm/types.hh"
+#include "params/IrisInterrupts.hh"
+
+void
+Iris::Interrupts::serialize(CheckpointOut &cp) const
+{
+    using namespace ArmISA;
+
+    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+    CPSR orig_cpsr = cpsr;
+    SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
+    SCR orig_scr = scr;
+    HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+    HCR orig_hcr = hcr;
+
+    // Set up state so we can get either physical or virtual interrupt bits.
+    cpsr.mode = 0;
+    cpsr.width = 0;
+    cpsr.el = EL1;
+    tc->setMiscReg(MISCREG_CPSR, cpsr);
+    scr.eel2 = 1;
+    tc->setMiscReg(MISCREG_SCR, scr);
+
+    // Get the virtual bits.
+    hcr.imo = 1;
+    hcr.fmo = 1;
+    hcr.amo = 1;
+    tc->setMiscReg(MISCREG_HCR_EL2, hcr);
+
+    RegVal isr_el1 = tc->readMiscRegNoEffect(MISCREG_ISR_EL1);
+    // There is also a virtual abort, but it's not used by gem5.
+    bool virt_irq = bits(7, isr_el1);
+    bool virt_fiq = bits(6, isr_el1);
+
+    // Get the physical bits.
+    hcr.imo = 0;
+    hcr.fmo = 0;
+    hcr.amo = 0;
+    tc->setMiscReg(MISCREG_HCR_EL2, hcr);
+
+    isr_el1 = tc->readMiscRegNoEffect(MISCREG_ISR_EL1);
+    bool phys_abort = bits(8, isr_el1);
+    bool phys_irq = bits(7, isr_el1);
+    bool phys_fiq = bits(6, isr_el1);
+
+    tc->setMiscReg(MISCREG_CPSR, orig_cpsr);
+    tc->setMiscReg(MISCREG_SCR_EL3, orig_scr);
+    tc->setMiscReg(MISCREG_HCR_EL2, orig_hcr);
+
+    bool interrupts[ArmISA::NumInterruptTypes];
+    uint64_t intStatus = 0;
+
+    for (bool &i: interrupts)
+        i = false;
+
+    interrupts[INT_ABT] = phys_abort;
+    interrupts[INT_IRQ] = phys_irq;
+    interrupts[INT_FIQ] = phys_fiq;
+    interrupts[INT_SEV] = tc->readMiscReg(MISCREG_SEV_MAILBOX);
+    interrupts[INT_VIRT_IRQ] = virt_irq;
+    interrupts[INT_VIRT_FIQ] = virt_fiq;
+
+    for (int i = 0; i < NumInterruptTypes; i++) {
+        if (interrupts[i])
+            intStatus |= (0x1ULL << i);
+    }
+
+    SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
+    SERIALIZE_SCALAR(intStatus);
+}
+
+void
+Iris::Interrupts::unserialize(CheckpointIn &cp)
+{
+}
+
+Iris::Interrupts *
+IrisInterruptsParams::create()
+{
+    return new Iris::Interrupts(this);
+}

src/arch/arm/fastmodel/iris/interrupts.hh

@@ -0,0 +1,63 @@
+/*
+ * Copyright 2019 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_ARM_FASTMODEL_IRIS_INTERRUPTS_HH__
+#define __ARCH_ARM_FASTMODEL_IRIS_INTERRUPTS_HH__
+
+#include "arch/arm/fastmodel/iris/thread_context.hh"
+#include "arch/generic/interrupts.hh"
+#include "params/IrisInterrupts.hh"
+
+namespace Iris
+{
+
+class Interrupts : public BaseInterrupts
+{
+  public:
+    typedef IrisInterruptsParams Params;
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    Interrupts(Params *p) : BaseInterrupts(p) {}
+
+    bool checkInterrupts() const override { return false; }
+    Fault getInterrupt() override { return NoFault; }
+    void updateIntrInfo() override {}
+
+    void clearAll() override {}
+
+    void serialize(CheckpointOut &cp) const override;
+    void unserialize(CheckpointIn &cp) override;
+};
+
+} // namespace Iris
+
+#endif // __ARCH_ARM_FASTMODEL_IRIS_INTERRUPTS_HH__