arch-mips: Replaced BigEndianByteOrder in MIPS
The following change removed the `BigEndianByteOrder` enum and replaced it with `ByteOrder:big`: https://gem5-review.googlesource.com/c/public/gem5/+/33174 This change was not propogated to `src/arch/mips/isa/decoder.isa` and `src/arch/mips/isa/formats/mem.isa`, and therefore caused compilation errors. This caused the Nightly Build to fail: https://www.mail-archive.com/gem5-dev@gem5.org/msg35900.html This commit fixes this error. Change-Id: I3967eb9e9236a7a95318c17ca410b613b8473eed Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34255 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
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@@ -1532,7 +1532,7 @@ decode OPCODE_HI default Unknown::unknown() {
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if (Rs<2:0> == 0) {
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Fd_ud = Fs_ud;
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} else if (Rs<2:0> == 4) {
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if (GuestByteOrder == BigEndianByteOrder)
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if (GuestByteOrder == ByteOrder::big)
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Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>;
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else
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Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
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@@ -497,7 +497,7 @@ def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
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uint32_t mem_word = Mem_uw;
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uint32_t unalign_addr = Rs + disp;
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uint32_t byte_offset = unalign_addr & 3;
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if (GuestByteOrder == BigEndianByteOrder)
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if (GuestByteOrder == ByteOrder::big)
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byte_offset ^= 3;
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'''
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@@ -515,7 +515,7 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
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uint32_t mem_word = 0;
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uint32_t unaligned_addr = Rs + disp;
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uint32_t byte_offset = unaligned_addr & 3;
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if (GuestByteOrder == BigEndianByteOrder)
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if (GuestByteOrder == ByteOrder::big)
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byte_offset ^= 3;
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fault = readMemAtomicLE(xc, traceData, EA, mem_word, memAccessFlags);
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'''
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