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arch-arm: Further clean up the AArch64 MSR/MRS decode

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This is just rearranging special cases bringing them together within
read/write switch statements

Change-Id: I170aea2a251167d41070e35bef13b41353de2342
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61690
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2022-07-26 15:22:56 +01:00
parent 5a65aae091
commit e3ff57e477
1 changed files with 18 additions and 18 deletions
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36
src/arch/arm/isa/formats/aarch64.isa
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@@ -459,14 +459,7 @@ namespace Aarch64
bool read = l;
MiscRegIndex miscReg =
decodeAArch64SysReg(op0, op1, crn, crm, op2);
if (read) {
if ((miscReg == MISCREG_DC_CIVAC_Xt) ||
(miscReg == MISCREG_DC_CVAC_Xt) ||
(miscReg == MISCREG_DC_IVAC_Xt) ||
(miscReg == MISCREG_DC_ZVA_Xt)) {
return new Unknown64(machInst);
}
}
// Check for invalid registers
if (miscReg == MISCREG_UNKNOWN) {
auto full_mnemonic =
@@ -489,19 +482,26 @@ namespace Aarch64
rt, read, full_mnemonic);
} else {
if (miscReg == MISCREG_NZCV) {
if (read)
return new MrsNZCV64(machInst, rt, miscReg);
else
return new MsrNZCV64(machInst, miscReg, rt);
}
if (read) {
StaticInstPtr si = new Mrs64(machInst, rt, miscReg);
if (lookUpMiscReg[miscReg].info[MISCREG_UNVERIFIABLE])
si->setFlag(StaticInst::IsUnverifiable);
return si;
switch (miscReg) {
case MISCREG_NZCV:
return new MrsNZCV64(machInst, rt, miscReg);
case MISCREG_DC_CIVAC_Xt:
case MISCREG_DC_CVAC_Xt:
case MISCREG_DC_IVAC_Xt:
case MISCREG_DC_ZVA_Xt:
return new Unknown64(machInst);
default: {
StaticInstPtr si = new Mrs64(machInst, rt, miscReg);
if (lookUpMiscReg[miscReg].info[MISCREG_UNVERIFIABLE])
si->setFlag(StaticInst::IsUnverifiable);
return si;
}
}
} else {
switch (miscReg) {
case MISCREG_NZCV:
return new MsrNZCV64(machInst, miscReg, rt);
case MISCREG_DC_ZVA_Xt:
return new Dczva(machInst, rt, miscReg);
case MISCREG_DC_CVAU_Xt: