tests: Removed "tests/quick"
Tests/resources contained within "tests/quick" have been migrated to the testlib framework. Change-Id: I49f2a469905f6fca5a36af433f84a5de4ec5c74f Issue-on: https://gem5.atlassian.net/browse/GEM5-109 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27727 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Bobby R. Bruce
File diff suppressed because it is too large
Load Diff
@@ -1,41 +0,0 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
|
||||
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
|
||||
warn: Returning zero for read from miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
@@ -1,32 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 1 2016 17:10:05
|
||||
gem5 started Aug 1 2016 17:37:31
|
||||
gem5 executing on e108600-lin, pid 13229
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
Exiting @ tick 2802883274000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,214 +0,0 @@
|
||||
Booting Linux on physical CPU 0x0
|
||||
|
||||
Initializing cgroup subsys cpuset
|
||||
|
||||
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
|
||||
|
||||
Kernel was built at commit id ''
|
||||
|
||||
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
|
||||
|
||||
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
|
||||
|
||||
Machine model: V2P-CA15
|
||||
|
||||
bootconsole [earlycon0] enabled
|
||||
|
||||
Memory policy: Data cache writealloc
|
||||
|
||||
kdebugv2m: Following are test values to confirm proper working
|
||||
|
||||
kdebugv2m: Ranges 42000000 0
|
||||
|
||||
kdebugv2m: Regs 30000000 1000000
|
||||
|
||||
kdebugv2m: Virtual-Reg f0000000
|
||||
|
||||
kdebugv2m: pci node addr_cells 3
|
||||
|
||||
kdebugv2m: pci node size_cells 2
|
||||
|
||||
kdebugv2m: motherboard addr_cells 2
|
||||
|
||||
On node 0 totalpages: 65536
|
||||
|
||||
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
|
||||
|
||||
Normal zone: 512 pages used for memmap
|
||||
|
||||
Normal zone: 0 pages reserved
|
||||
|
||||
Normal zone: 65536 pages, LIFO batch:15
|
||||
|
||||
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
|
||||
|
||||
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
|
||||
|
||||
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
|
||||
|
||||
pcpu-alloc: [0] 0 [0] 1
|
||||
|
||||
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
|
||||
|
||||
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
|
||||
PID hash table entries: 1024 (order: 0, 4096 bytes)
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
|
||||
|
||||
Memory: 235656K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26488K reserved, 0K highmem)
|
||||
|
||||
Virtual kernel memory layout:
|
||||
|
||||
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
|
||||
|
||||
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
|
||||
|
||||
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
|
||||
|
||||
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
|
||||
|
||||
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
|
||||
|
||||
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
|
||||
|
||||
.text : 0x80008000 - 0x806a942c (6790 kB)
|
||||
|
||||
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
|
||||
|
||||
.data : 0x806f4000 - 0x80732754 ( 250 kB)
|
||||
|
||||
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
|
||||
|
||||
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
|
||||
|
||||
Preemptible hierarchical RCU implementation.
|
||||
|
||||
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
|
||||
|
||||
NR_IRQS:16 nr_irqs:16 16
|
||||
|
||||
Architected cp15 timer(s) running at 25.16MHz (phys).
|
||||
|
||||
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
|
||||
|
||||
Switching to timer-based delay loop
|
||||
|
||||
Console: colour dummy device 80x30
|
||||
|
||||
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
|
||||
pid_max: default: 32768 minimum: 301
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
CPU: Testing write buffer coherency: ok
|
||||
|
||||
/cpus/cpu@1 missing clock-frequency property
|
||||
|
||||
CPU0: update cpu_power 1024
|
||||
|
||||
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
|
||||
|
||||
Setting up static identity map for 0x804fee68 - 0x804fee9c
|
||||
|
||||
CPU1: Booted secondary processor
|
||||
|
||||
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
|
||||
|
||||
Brought up 2 CPUs
|
||||
|
||||
SMP: Total of 2 processors activated.
|
||||
|
||||
CPU: All CPU(s) started in SVC mode.
|
||||
|
||||
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
DMA: preallocated 256 KiB pool for atomic coherent allocations
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: CPU 1 failed to disable vector catch
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
|
||||
|
||||
Serial: AMBA PL011 UART driver
|
||||
|
||||
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
|
||||
console [ttyAMA0] enabled
|
||||
console [ttyAMA0] enabled
|
||||
|
||||
bootconsole [earlycon0] disabled
|
||||
bootconsole [earlycon0] disabled
|
||||
|
||||
PCI host bridge to bus 0000:00
|
||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
PCI: bus0: Fast back to back transfers disabled
|
||||
pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
|
||||
pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
|
||||
pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
|
||||
pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
|
||||
pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
|
||||
pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
|
||||
PCI map irq: slot 0, pin 1, devslot 0, irq: 68
|
||||
PCI map irq: slot 1, pin 2, devslot 1, irq: 69
|
||||
bio: create slab <bio-0> at 0
|
||||
vgaarb: loaded
|
||||
SCSI subsystem initialized
|
||||
libata version 3.00 loaded.
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
pps_core: LinuxPPS API ver. 1 registered
|
||||
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
PTP clock support registered
|
||||
Advanced Linux Sound Architecture Driver Initialized.
|
||||
Switched to clocksource arch_sys_counter
|
||||
NET: Registered protocol family 2
|
||||
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
|
||||
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
TCP: Hash tables configured (established 2048 bind 2048)
|
||||
TCP: reno registered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,33 +0,0 @@
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
|
||||
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
|
||||
warn: Returning zero for read from miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
@@ -1,32 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 1 2016 17:10:05
|
||||
gem5 started Aug 1 2016 17:10:34
|
||||
gem5 executing on e108600-lin, pid 12206
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
Exiting @ tick 2783855034000 because m5_exit instruction encountered
|
||||
@@ -1,829 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.783856 # Number of seconds simulated
|
||||
sim_ticks 2783855588000 # Number of ticks simulated
|
||||
final_tick 2783855588000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1539062 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1873561 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 30009675812 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 581968 # Number of bytes of host memory used
|
||||
host_seconds 92.77 # Real time elapsed on the host
|
||||
sim_insts 142771499 # Number of instructions simulated
|
||||
sim_ops 173801409 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3708849 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4142976 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3175774 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3182069 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3175774 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3715144 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7325045 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 10028 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
|
||||
system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 31525952 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8580 # DTB read misses
|
||||
system.cpu.dtb.write_hits 23124113 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1448 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 31534532 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125561 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 54650065 # DTB hits
|
||||
system.cpu.dtb.misses 10028 # DTB misses
|
||||
system.cpu.dtb.accesses 54660093 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 4762 # Table walker walks requested
|
||||
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
|
||||
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
|
||||
system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
|
||||
system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
|
||||
system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
|
||||
system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
|
||||
system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 147038008 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 147042770 # ITB inst accesses
|
||||
system.cpu.itb.hits 147038008 # DTB hits
|
||||
system.cpu.itb.misses 4762 # DTB misses
|
||||
system.cpu.itb.accesses 147042770 # DTB accesses
|
||||
system.cpu.numPwrStateTransitions 6160 # Number of power state transitions
|
||||
system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 874939855.098377 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 17329944394.226795 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateResidencyTicks::ON 89040834297 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814753703 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 5567714257 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142771499 # Number of instructions committed
|
||||
system.cpu.committedOps 173801409 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153161120 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 16873932 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730256 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153161120 # number of integer instructions
|
||||
system.cpu.num_fp_insts 11484 # number of float instructions
|
||||
system.cpu.num_int_register_reads 285043874 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107178310 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 530848973 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62363815 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55938612 # number of memory refs
|
||||
system.cpu.num_load_insts 31855576 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083036 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389632489.859149 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178081767.140850 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
|
||||
system.cpu.Branches 36396926 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121151851 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31852868 17.97% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24074264 13.58% 99.99% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMemRead 2708 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMemWrite 8772 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177218242 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 819384 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53783890 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819896 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.598430 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 219235120 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219235120 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30128814 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30128814 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22339797 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22339797 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 52468611 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52468611 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52863678 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52863678 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396270 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396270 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301666 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301666 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 697936 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697936 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814055 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814055 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641463 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641463 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53166547 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53166547 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53677733 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53677733 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227156 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227156 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018483 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018483 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.013127 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.013127 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 682141 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682141 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 1698986 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145341611 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699498 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.520319 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 148740619 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148740619 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145341611 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145341611 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145341611 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145341611 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145341611 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145341611 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699504 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699504 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699504 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699504 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699504 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699504 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147041115 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147041115 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147041115 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147041115 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147041115 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147041115 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 1698986 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1698986 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 109914 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65246.862425 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4827677 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175340 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 27.533233 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.133245 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734054 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 40257153 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40257153 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682141 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682141 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1666986 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1666986 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 152792 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 152792 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681189 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1681189 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505433 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 505433 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681189 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 658225 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2347799 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681189 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 658225 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2347799 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 146119 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 146119 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 15568 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 161687 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 179994 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 161687 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 179994 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682141 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682141 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1666986 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1666986 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298911 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 298911 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699487 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 1699487 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521001 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 521001 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699487 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819912 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2527793 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699487 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819912 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2527793 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.197200 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071206 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.197200 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071206 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101949 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5059862 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540459 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39267 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 427 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 427 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288305 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682141 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1698986 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 137243 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298911 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298911 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699504 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521001 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116038 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581944 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7753408 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 313964445 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 115353 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 6542464 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5251071 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018719 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.135530 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5152778 98.13% 98.13% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98293 1.87% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5251071 # Request fanout histogram
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 59002 # Transaction distribution
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.replacements 36430 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.909895 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909895 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 328176 # Number of data accesses
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 36464 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 36464 # number of overall misses
|
||||
system.iocache.overall_misses::total 36464 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
||||
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.membus.snoop_filter.tot_requests 362813 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 151005 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 40087 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8205 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 130 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 145998 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 145998 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497830 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605190 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 714548 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 430446 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.012887 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.112786 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 424899 98.71% 98.71% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 5547 1.29% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 430446 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
||||
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
||||
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
||||
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
||||
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,208 +0,0 @@
|
||||
Booting Linux on physical CPU 0x0
|
||||
|
||||
Initializing cgroup subsys cpuset
|
||||
|
||||
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
|
||||
|
||||
Kernel was built at commit id ''
|
||||
|
||||
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
|
||||
|
||||
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
|
||||
|
||||
Machine model: V2P-CA15
|
||||
|
||||
bootconsole [earlycon0] enabled
|
||||
|
||||
Memory policy: Data cache writealloc
|
||||
|
||||
kdebugv2m: Following are test values to confirm proper working
|
||||
|
||||
kdebugv2m: Ranges 42000000 0
|
||||
|
||||
kdebugv2m: Regs 30000000 1000000
|
||||
|
||||
kdebugv2m: Virtual-Reg f0000000
|
||||
|
||||
kdebugv2m: pci node addr_cells 3
|
||||
|
||||
kdebugv2m: pci node size_cells 2
|
||||
|
||||
kdebugv2m: motherboard addr_cells 2
|
||||
|
||||
On node 0 totalpages: 65536
|
||||
|
||||
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
|
||||
|
||||
Normal zone: 512 pages used for memmap
|
||||
|
||||
Normal zone: 0 pages reserved
|
||||
|
||||
Normal zone: 65536 pages, LIFO batch:15
|
||||
|
||||
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
|
||||
|
||||
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
|
||||
|
||||
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
|
||||
|
||||
pcpu-alloc: [0] 0
|
||||
|
||||
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
|
||||
|
||||
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
|
||||
PID hash table entries: 1024 (order: 0, 4096 bytes)
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
|
||||
|
||||
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
|
||||
|
||||
Virtual kernel memory layout:
|
||||
|
||||
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
|
||||
|
||||
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
|
||||
|
||||
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
|
||||
|
||||
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
|
||||
|
||||
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
|
||||
|
||||
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
|
||||
|
||||
.text : 0x80008000 - 0x806a942c (6790 kB)
|
||||
|
||||
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
|
||||
|
||||
.data : 0x806f4000 - 0x80732754 ( 250 kB)
|
||||
|
||||
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
|
||||
|
||||
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
|
||||
|
||||
Preemptible hierarchical RCU implementation.
|
||||
|
||||
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
|
||||
|
||||
NR_IRQS:16 nr_irqs:16 16
|
||||
|
||||
Architected cp15 timer(s) running at 25.16MHz (phys).
|
||||
|
||||
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
|
||||
|
||||
Switching to timer-based delay loop
|
||||
|
||||
Console: colour dummy device 80x30
|
||||
|
||||
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
|
||||
pid_max: default: 32768 minimum: 301
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
CPU: Testing write buffer coherency: ok
|
||||
|
||||
CPU0: update cpu_power 1024
|
||||
|
||||
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
|
||||
|
||||
Setting up static identity map for 0x804fee68 - 0x804fee9c
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated.
|
||||
|
||||
CPU: All CPU(s) started in SVC mode.
|
||||
|
||||
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
DMA: preallocated 256 KiB pool for atomic coherent allocations
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: CPU 0 failed to disable vector catch
|
||||
|
||||
Serial: AMBA PL011 UART driver
|
||||
|
||||
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
|
||||
console [ttyAMA0] enabled
|
||||
console [ttyAMA0] enabled
|
||||
|
||||
bootconsole [earlycon0] disabled
|
||||
bootconsole [earlycon0] disabled
|
||||
|
||||
PCI host bridge to bus 0000:00
|
||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
PCI: bus0: Fast back to back transfers disabled
|
||||
pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
|
||||
pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
|
||||
pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
|
||||
pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
|
||||
pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
|
||||
pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
|
||||
PCI map irq: slot 0, pin 1, devslot 0, irq: 68
|
||||
PCI map irq: slot 1, pin 2, devslot 1, irq: 69
|
||||
bio: create slab <bio-0> at 0
|
||||
vgaarb: loaded
|
||||
SCSI subsystem initialized
|
||||
libata version 3.00 loaded.
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
pps_core: LinuxPPS API ver. 1 registered
|
||||
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
PTP clock support registered
|
||||
Advanced Linux Sound Architecture Driver Initialized.
|
||||
Switched to clocksource arch_sys_counter
|
||||
NET: Registered protocol family 2
|
||||
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
|
||||
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
TCP: Hash tables configured (established 2048 bind 2048)
|
||||
TCP: reno registered
|
||||
UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
NET: Registered protocol family 1
|
||||
RPC: Registered named UNIX socket transport module.
|
||||
RPC: Registered udp transport module.
|
||||
RPC: Registered tcp transport module.
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,62 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
|
||||
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
|
||||
warn: Returning zero for read from miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
@@ -1,12 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 29 2017 18:44:23
|
||||
gem5 started Mar 29 2017 18:44:38
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 53279
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2871012355500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,214 +0,0 @@
|
||||
Booting Linux on physical CPU 0x0
|
||||
|
||||
Initializing cgroup subsys cpuset
|
||||
|
||||
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
|
||||
|
||||
Kernel was built at commit id ''
|
||||
|
||||
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
|
||||
|
||||
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
|
||||
|
||||
Machine model: V2P-CA15
|
||||
|
||||
bootconsole [earlycon0] enabled
|
||||
|
||||
Memory policy: Data cache writealloc
|
||||
|
||||
kdebugv2m: Following are test values to confirm proper working
|
||||
|
||||
kdebugv2m: Ranges 42000000 0
|
||||
|
||||
kdebugv2m: Regs 30000000 1000000
|
||||
|
||||
kdebugv2m: Virtual-Reg f0000000
|
||||
|
||||
kdebugv2m: pci node addr_cells 3
|
||||
|
||||
kdebugv2m: pci node size_cells 2
|
||||
|
||||
kdebugv2m: motherboard addr_cells 2
|
||||
|
||||
On node 0 totalpages: 65536
|
||||
|
||||
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
|
||||
|
||||
Normal zone: 512 pages used for memmap
|
||||
|
||||
Normal zone: 0 pages reserved
|
||||
|
||||
Normal zone: 65536 pages, LIFO batch:15
|
||||
|
||||
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
|
||||
|
||||
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
|
||||
|
||||
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
|
||||
|
||||
pcpu-alloc: [0] 0 [0] 1
|
||||
|
||||
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
|
||||
|
||||
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
|
||||
PID hash table entries: 1024 (order: 0, 4096 bytes)
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
|
||||
|
||||
Memory: 235656K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26488K reserved, 0K highmem)
|
||||
|
||||
Virtual kernel memory layout:
|
||||
|
||||
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
|
||||
|
||||
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
|
||||
|
||||
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
|
||||
|
||||
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
|
||||
|
||||
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
|
||||
|
||||
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
|
||||
|
||||
.text : 0x80008000 - 0x806a942c (6790 kB)
|
||||
|
||||
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
|
||||
|
||||
.data : 0x806f4000 - 0x80732754 ( 250 kB)
|
||||
|
||||
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
|
||||
|
||||
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
|
||||
|
||||
Preemptible hierarchical RCU implementation.
|
||||
|
||||
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
|
||||
|
||||
NR_IRQS:16 nr_irqs:16 16
|
||||
|
||||
Architected cp15 timer(s) running at 25.16MHz (phys).
|
||||
|
||||
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
|
||||
|
||||
Switching to timer-based delay loop
|
||||
|
||||
Console: colour dummy device 80x30
|
||||
|
||||
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
|
||||
pid_max: default: 32768 minimum: 301
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
CPU: Testing write buffer coherency: ok
|
||||
|
||||
/cpus/cpu@1 missing clock-frequency property
|
||||
|
||||
CPU0: update cpu_power 1024
|
||||
|
||||
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
|
||||
|
||||
Setting up static identity map for 0x804fee68 - 0x804fee9c
|
||||
|
||||
CPU1: Booted secondary processor
|
||||
|
||||
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
|
||||
|
||||
Brought up 2 CPUs
|
||||
|
||||
SMP: Total of 2 processors activated.
|
||||
|
||||
CPU: All CPU(s) started in SVC mode.
|
||||
|
||||
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
DMA: preallocated 256 KiB pool for atomic coherent allocations
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: CPU 1 failed to disable vector catch
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
|
||||
|
||||
Serial: AMBA PL011 UART driver
|
||||
|
||||
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
|
||||
console [ttyAMA0] enabled
|
||||
console [ttyAMA0] enabled
|
||||
|
||||
bootconsole [earlycon0] disabled
|
||||
bootconsole [earlycon0] disabled
|
||||
|
||||
PCI host bridge to bus 0000:00
|
||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
PCI: bus0: Fast back to back transfers disabled
|
||||
pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
|
||||
pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
|
||||
pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
|
||||
pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
|
||||
pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
|
||||
pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
|
||||
PCI map irq: slot 0, pin 1, devslot 0, irq: 68
|
||||
PCI map irq: slot 1, pin 2, devslot 1, irq: 69
|
||||
bio: create slab <bio-0> at 0
|
||||
vgaarb: loaded
|
||||
SCSI subsystem initialized
|
||||
libata version 3.00 loaded.
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
pps_core: LinuxPPS API ver. 1 registered
|
||||
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
PTP clock support registered
|
||||
Advanced Linux Sound Architecture Driver Initialized.
|
||||
Switched to clocksource arch_sys_counter
|
||||
NET: Registered protocol family 2
|
||||
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
|
||||
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
TCP: Hash tables configured (established 2048 bind 2048)
|
||||
TCP: reno registered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,54 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
|
||||
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
|
||||
warn: Returning zero for read from miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
@@ -1,12 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 29 2017 18:44:23
|
||||
gem5 started Mar 29 2017 18:44:38
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 53278
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2905305537500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,208 +0,0 @@
|
||||
Booting Linux on physical CPU 0x0
|
||||
|
||||
Initializing cgroup subsys cpuset
|
||||
|
||||
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
|
||||
|
||||
Kernel was built at commit id ''
|
||||
|
||||
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
|
||||
|
||||
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
|
||||
|
||||
Machine model: V2P-CA15
|
||||
|
||||
bootconsole [earlycon0] enabled
|
||||
|
||||
Memory policy: Data cache writealloc
|
||||
|
||||
kdebugv2m: Following are test values to confirm proper working
|
||||
|
||||
kdebugv2m: Ranges 42000000 0
|
||||
|
||||
kdebugv2m: Regs 30000000 1000000
|
||||
|
||||
kdebugv2m: Virtual-Reg f0000000
|
||||
|
||||
kdebugv2m: pci node addr_cells 3
|
||||
|
||||
kdebugv2m: pci node size_cells 2
|
||||
|
||||
kdebugv2m: motherboard addr_cells 2
|
||||
|
||||
On node 0 totalpages: 65536
|
||||
|
||||
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
|
||||
|
||||
Normal zone: 512 pages used for memmap
|
||||
|
||||
Normal zone: 0 pages reserved
|
||||
|
||||
Normal zone: 65536 pages, LIFO batch:15
|
||||
|
||||
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
|
||||
|
||||
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
|
||||
|
||||
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
|
||||
|
||||
pcpu-alloc: [0] 0
|
||||
|
||||
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
|
||||
|
||||
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
|
||||
PID hash table entries: 1024 (order: 0, 4096 bytes)
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
|
||||
|
||||
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
|
||||
|
||||
Virtual kernel memory layout:
|
||||
|
||||
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
|
||||
|
||||
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
|
||||
|
||||
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
|
||||
|
||||
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
|
||||
|
||||
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
|
||||
|
||||
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
|
||||
|
||||
.text : 0x80008000 - 0x806a942c (6790 kB)
|
||||
|
||||
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
|
||||
|
||||
.data : 0x806f4000 - 0x80732754 ( 250 kB)
|
||||
|
||||
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
|
||||
|
||||
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
|
||||
|
||||
Preemptible hierarchical RCU implementation.
|
||||
|
||||
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
|
||||
|
||||
NR_IRQS:16 nr_irqs:16 16
|
||||
|
||||
Architected cp15 timer(s) running at 25.16MHz (phys).
|
||||
|
||||
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
|
||||
|
||||
Switching to timer-based delay loop
|
||||
|
||||
Console: colour dummy device 80x30
|
||||
|
||||
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
|
||||
pid_max: default: 32768 minimum: 301
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
CPU: Testing write buffer coherency: ok
|
||||
|
||||
CPU0: update cpu_power 1024
|
||||
|
||||
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
|
||||
|
||||
Setting up static identity map for 0x804fee68 - 0x804fee9c
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated.
|
||||
|
||||
CPU: All CPU(s) started in SVC mode.
|
||||
|
||||
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
DMA: preallocated 256 KiB pool for atomic coherent allocations
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: CPU 0 failed to disable vector catch
|
||||
|
||||
Serial: AMBA PL011 UART driver
|
||||
|
||||
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
|
||||
console [ttyAMA0] enabled
|
||||
console [ttyAMA0] enabled
|
||||
|
||||
bootconsole [earlycon0] disabled
|
||||
bootconsole [earlycon0] disabled
|
||||
|
||||
PCI host bridge to bus 0000:00
|
||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
PCI: bus0: Fast back to back transfers disabled
|
||||
pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
|
||||
pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
|
||||
pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
|
||||
pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
|
||||
pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
|
||||
pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
|
||||
PCI map irq: slot 0, pin 1, devslot 0, irq: 68
|
||||
PCI map irq: slot 1, pin 2, devslot 1, irq: 69
|
||||
bio: create slab <bio-0> at 0
|
||||
vgaarb: loaded
|
||||
SCSI subsystem initialized
|
||||
libata version 3.00 loaded.
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
pps_core: LinuxPPS API ver. 1 registered
|
||||
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
PTP clock support registered
|
||||
Advanced Linux Sound Architecture Driver Initialized.
|
||||
Switched to clocksource arch_sys_counter
|
||||
NET: Registered protocol family 2
|
||||
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
|
||||
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
TCP: Hash tables configured (established 2048 bind 2048)
|
||||
TCP: reno registered
|
||||
UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
NET: Registered protocol family 1
|
||||
RPC: Registered named UNIX socket transport module.
|
||||
RPC: Registered udp transport module.
|
||||
RPC: Registered tcp transport module.
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,8 +0,0 @@
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
@@ -1,13 +0,0 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 21 2016 14:41:03
|
||||
gem5 started Jan 21 2016 14:41:54
|
||||
gem5 executing on zizzer, pid 17910
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5112152301500 because m5_exit instruction encountered
|
||||
@@ -1,649 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.112152 # Number of seconds simulated
|
||||
sim_ticks 5112151729000 # Number of ticks simulated
|
||||
final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1314225 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2690507 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33581335470 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 609616 # Number of bytes of host memory used
|
||||
host_seconds 152.23 # Real time elapsed on the host
|
||||
sim_insts 200067055 # Number of instructions simulated
|
||||
sim_ops 409581065 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 846912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10615104 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11490752 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 846912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 846912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 9269888 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9269888 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 13233 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165861 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 179543 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 144842 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144842 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 165666 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2076445 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2247733 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 165666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 165666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1813305 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1813305 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1813305 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 165666 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2076445 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4061038 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.numCycles 10224307424 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 200067055 # Number of instructions committed
|
||||
system.cpu.committedOps 409581065 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374584177 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 2308905 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 40001120 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374584177 # number of integer instructions
|
||||
system.cpu.num_fp_insts 48 # number of float instructions
|
||||
system.cpu.num_int_register_reads 682690924 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 323558192 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 48 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 233837631 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 157316591 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 35667176 # number of memory refs
|
||||
system.cpu.num_load_insts 27243343 # Number of load instructions
|
||||
system.cpu.num_store_insts 8423833 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770322790.617842 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453984633.382158 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044402 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955598 # Percentage of idle cycles
|
||||
system.cpu.Branches 43152262 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 172765 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 373477070 91.18% 91.23% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 144574 0.04% 91.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 123086 0.03% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 16 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27240752 6.65% 97.94% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 8423833 2.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 409582096 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1621909 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 20181333 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1622421 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.439024 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 88837527 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 88837527 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12023410 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12023410 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8096819 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8096819 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 58904 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 58904 # number of SoftPFReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20120229 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20120229 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20179133 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20179133 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 905268 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 905268 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 316618 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 316618 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 402753 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 402753 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1221886 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1221886 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624639 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624639 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 12928678 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 12928678 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8413437 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8413437 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461657 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 461657 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21342115 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21342115 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21803772 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21803772 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070020 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.070020 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037632 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037632 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872407 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872407 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.057252 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.057252 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074512 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074512 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 1535790 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1535790 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014001 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12936 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.666366 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100450626500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014001 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313375 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
|
||||
system.cpu.dtb_walker_cache.tags.tag_accesses 52745 # Number of tag accesses
|
||||
system.cpu.dtb_walker_cache.tags.data_accesses 52745 # Number of data accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12937 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12937 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12937 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12937 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12937 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12937 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8957 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8957 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8957 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8957 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8957 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8957 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409108 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409108 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409108 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409108 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409108 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409108 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2897 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2897 # number of writebacks
|
||||
system.cpu.icache.tags.replacements 792340 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 243675443 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 792852 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 307.340390 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 245261161 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 245261161 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243675443 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243675443 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243675443 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243675443 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243675443 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243675443 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 792859 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 792859 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 792859 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 792859 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 792859 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 792859 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244468302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244468302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244468302 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244468302 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244468302 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244468302 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 792340 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 792340 # number of writebacks
|
||||
system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026555 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5102137159500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026555 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189160 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189160 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
|
||||
system.cpu.itb_walker_cache.tags.tag_accesses 28899 # Number of tag accesses
|
||||
system.cpu.itb_walker_cache.tags.data_accesses 28899 # Number of data accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7765 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 7765 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7767 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::total 7767 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7767 # number of overall hits
|
||||
system.cpu.itb_walker_cache.overall_hits::total 7767 # number of overall hits
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.364566 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.364566 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.364507 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::total 0.364507 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.364507 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::total 0.364507 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks
|
||||
system.cpu.l2cache.tags.replacements 106202 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64823.935074 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4340729 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.509391 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51928.967732 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135114 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.317021 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.512729 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792373 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037511 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159249 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63960 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20880 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39442 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975952 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 39254568 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 39254568 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1539387 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1539387 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 792329 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 792329 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 312 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 312 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179766 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179766 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779612 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 779612 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6533 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2871 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275070 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1284474 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6533 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2871 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 779612 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1454836 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2243852 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6533 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2871 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 779612 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1454836 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2243852 # number of overall hits
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1349 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1349 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134647 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134647 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13234 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13234 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32164 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 32170 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13234 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166811 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 180051 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13234 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166811 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 180051 # number of overall misses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1539387 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1539387 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 792329 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 792329 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1661 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1661 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314413 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314413 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 792846 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 792846 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6534 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2876 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307234 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1316644 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6534 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2876 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 792846 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1621647 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2423903 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6534 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2876 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 792846 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1621647 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2423903 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.812161 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.812161 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428249 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428249 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016692 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016692 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000153 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001739 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024605 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024433 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000153 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001739 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016692 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102865 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074281 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000153 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001739 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016692 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102865 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074281 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 98175 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98175 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4856494 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425336 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 15971629 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1539387 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 792340 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 93857 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2200 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2200 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 314418 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 314418 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 792859 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321433 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378058 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613747 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 35029964 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101452736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227551417 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 329920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 758656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 330092729 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 203468 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18930863 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18911304 99.90% 99.90% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18930863 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 57724 # Transaction distribution
|
||||
system.iobus.trans_dist::MessageReq 1696 # Transaction distribution
|
||||
system.iobus.trans_dist::MessageResp 1696 # Transaction distribution
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27940 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::total 20044316 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 20142954 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13970 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::total 10028276 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 13062828 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.replacements 47568 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.042439 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4994875253009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042439 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002652 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.002652 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 428607 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 428607 # Number of data accesses
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47623 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses
|
||||
system.iocache.overall_misses::total 47623 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
||||
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
||||
system.iocache.writebacks::total 46667 # number of writebacks
|
||||
system.membus.trans_dist::ReadReq 13857337 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 13903644 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 13943 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 144842 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8802 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 2189 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 1650 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 134346 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 134346 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 46307 # Transaction distribution
|
||||
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
|
||||
system.membus.trans_dist::MessageResp 1696 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
|
||||
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 469415 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28211975 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 28358181 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43211961 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 46263225 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 14256182 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.010907 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 14254486 99.99% 99.99% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 14256182 # Request fanout histogram
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
||||
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,9 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
@@ -1,13 +0,0 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 21 2016 14:41:03
|
||||
gem5 started Jan 21 2016 14:41:53
|
||||
gem5 executing on zizzer, pid 17907
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5194947216500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,27 +0,0 @@
|
||||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
root.system.readfile = os.path.join(tests_root, 'halt.sh')
|
||||
@@ -1,26 +0,0 @@
|
||||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
@@ -1,42 +0,0 @@
|
||||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
# workload
|
||||
benchmarks = [
|
||||
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
|
||||
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
|
||||
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
|
||||
"tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
|
||||
]
|
||||
|
||||
for i, cpu in zip(range(len(cpus)), root.system.cpu):
|
||||
p = Process()
|
||||
p.executable = benchmarks[i*2]
|
||||
p.cmd = benchmarks[(i*2)+1]
|
||||
root.system.cpu[i].workload = p
|
||||
root.system.cpu[i].max_insts_all_threads = 10000000
|
||||
#root.system.cpu.workload = Process(cmd = 'hello',
|
||||
# executable = binpath('hello'))
|
||||
@@ -1,31 +0,0 @@
|
||||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
process1 = Process(cmd = 'hello', executable = binpath('hello'), pid = 100)
|
||||
process2 = Process(cmd = 'hello', executable = binpath('hello'),
|
||||
pid = 101, ppid = 100)
|
||||
|
||||
root.system.cpu[0].workload = [process1, process2]
|
||||
@@ -1,381 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler mem_ctrl membus
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.mem_ctrl
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[2]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
children=voltage_domain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.clk_domain.voltage_domain
|
||||
|
||||
[system.clk_domain.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=-1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[1]
|
||||
icache_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=tests/test-progs/hello/bin/arm/linux/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.mem_ctrl]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:536870911:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.mem_ctrl.port
|
||||
slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
@@ -1,14 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 17:55:48
|
||||
gem5 started Apr 3 2017 18:05:51
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55329
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Beginning simulation!
|
||||
Hello world!
|
||||
Exiting @ tick 372284000 because exiting with last active thread context
|
||||
@@ -1,510 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000372
|
||||
sim_ticks 372284000
|
||||
final_tick 372284000
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 111411
|
||||
host_op_rate 128815
|
||||
host_tick_rate 8307715104
|
||||
host_mem_usage 662496
|
||||
host_seconds 0.05
|
||||
sim_insts 4988
|
||||
sim_ops 5770
|
||||
system.clk_domain.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000
|
||||
system.mem_ctrl.bytes_read::cpu.inst 20108
|
||||
system.mem_ctrl.bytes_read::cpu.data 4672
|
||||
system.mem_ctrl.bytes_read::total 24780
|
||||
system.mem_ctrl.bytes_inst_read::cpu.inst 20108
|
||||
system.mem_ctrl.bytes_inst_read::total 20108
|
||||
system.mem_ctrl.bytes_written::cpu.data 3696
|
||||
system.mem_ctrl.bytes_written::total 3696
|
||||
system.mem_ctrl.num_reads::cpu.inst 5027
|
||||
system.mem_ctrl.num_reads::cpu.data 1061
|
||||
system.mem_ctrl.num_reads::total 6088
|
||||
system.mem_ctrl.num_writes::cpu.data 936
|
||||
system.mem_ctrl.num_writes::total 936
|
||||
system.mem_ctrl.bw_read::cpu.inst 54012528
|
||||
system.mem_ctrl.bw_read::cpu.data 12549559
|
||||
system.mem_ctrl.bw_read::total 66562087
|
||||
system.mem_ctrl.bw_inst_read::cpu.inst 54012528
|
||||
system.mem_ctrl.bw_inst_read::total 54012528
|
||||
system.mem_ctrl.bw_write::cpu.data 9927905
|
||||
system.mem_ctrl.bw_write::total 9927905
|
||||
system.mem_ctrl.bw_total::cpu.inst 54012528
|
||||
system.mem_ctrl.bw_total::cpu.data 22477463
|
||||
system.mem_ctrl.bw_total::total 76489992
|
||||
system.mem_ctrl.readReqs 6089
|
||||
system.mem_ctrl.writeReqs 936
|
||||
system.mem_ctrl.readBursts 6089
|
||||
system.mem_ctrl.writeBursts 936
|
||||
system.mem_ctrl.bytesReadDRAM 383296
|
||||
system.mem_ctrl.bytesReadWrQ 6400
|
||||
system.mem_ctrl.bytesWritten 4096
|
||||
system.mem_ctrl.bytesReadSys 24784
|
||||
system.mem_ctrl.bytesWrittenSys 3696
|
||||
system.mem_ctrl.servicedByWrQ 100
|
||||
system.mem_ctrl.mergedWrBursts 855
|
||||
system.mem_ctrl.neitherReadNorWriteReqs 0
|
||||
system.mem_ctrl.perBankRdBursts::0 911
|
||||
system.mem_ctrl.perBankRdBursts::1 1454
|
||||
system.mem_ctrl.perBankRdBursts::2 724
|
||||
system.mem_ctrl.perBankRdBursts::3 364
|
||||
system.mem_ctrl.perBankRdBursts::4 505
|
||||
system.mem_ctrl.perBankRdBursts::5 303
|
||||
system.mem_ctrl.perBankRdBursts::6 487
|
||||
system.mem_ctrl.perBankRdBursts::7 206
|
||||
system.mem_ctrl.perBankRdBursts::8 42
|
||||
system.mem_ctrl.perBankRdBursts::9 155
|
||||
system.mem_ctrl.perBankRdBursts::10 192
|
||||
system.mem_ctrl.perBankRdBursts::11 422
|
||||
system.mem_ctrl.perBankRdBursts::12 108
|
||||
system.mem_ctrl.perBankRdBursts::13 36
|
||||
system.mem_ctrl.perBankRdBursts::14 0
|
||||
system.mem_ctrl.perBankRdBursts::15 80
|
||||
system.mem_ctrl.perBankWrBursts::0 0
|
||||
system.mem_ctrl.perBankWrBursts::1 0
|
||||
system.mem_ctrl.perBankWrBursts::2 0
|
||||
system.mem_ctrl.perBankWrBursts::3 0
|
||||
system.mem_ctrl.perBankWrBursts::4 0
|
||||
system.mem_ctrl.perBankWrBursts::5 0
|
||||
system.mem_ctrl.perBankWrBursts::6 0
|
||||
system.mem_ctrl.perBankWrBursts::7 0
|
||||
system.mem_ctrl.perBankWrBursts::8 0
|
||||
system.mem_ctrl.perBankWrBursts::9 0
|
||||
system.mem_ctrl.perBankWrBursts::10 13
|
||||
system.mem_ctrl.perBankWrBursts::11 46
|
||||
system.mem_ctrl.perBankWrBursts::12 5
|
||||
system.mem_ctrl.perBankWrBursts::13 0
|
||||
system.mem_ctrl.perBankWrBursts::14 0
|
||||
system.mem_ctrl.perBankWrBursts::15 0
|
||||
system.mem_ctrl.numRdRetry 0
|
||||
system.mem_ctrl.numWrRetry 0
|
||||
system.mem_ctrl.totGap 372207000
|
||||
system.mem_ctrl.readPktSize::0 70
|
||||
system.mem_ctrl.readPktSize::1 1
|
||||
system.mem_ctrl.readPktSize::2 5858
|
||||
system.mem_ctrl.readPktSize::3 160
|
||||
system.mem_ctrl.readPktSize::4 0
|
||||
system.mem_ctrl.readPktSize::5 0
|
||||
system.mem_ctrl.readPktSize::6 0
|
||||
system.mem_ctrl.writePktSize::0 16
|
||||
system.mem_ctrl.writePktSize::1 0
|
||||
system.mem_ctrl.writePktSize::2 920
|
||||
system.mem_ctrl.writePktSize::3 0
|
||||
system.mem_ctrl.writePktSize::4 0
|
||||
system.mem_ctrl.writePktSize::5 0
|
||||
system.mem_ctrl.writePktSize::6 0
|
||||
system.mem_ctrl.rdQLenPdf::0 5980
|
||||
system.mem_ctrl.rdQLenPdf::1 9
|
||||
system.mem_ctrl.rdQLenPdf::2 0
|
||||
system.mem_ctrl.rdQLenPdf::3 0
|
||||
system.mem_ctrl.rdQLenPdf::4 0
|
||||
system.mem_ctrl.rdQLenPdf::5 0
|
||||
system.mem_ctrl.rdQLenPdf::6 0
|
||||
system.mem_ctrl.rdQLenPdf::7 0
|
||||
system.mem_ctrl.rdQLenPdf::8 0
|
||||
system.mem_ctrl.rdQLenPdf::9 0
|
||||
system.mem_ctrl.rdQLenPdf::10 0
|
||||
system.mem_ctrl.rdQLenPdf::11 0
|
||||
system.mem_ctrl.rdQLenPdf::12 0
|
||||
system.mem_ctrl.rdQLenPdf::13 0
|
||||
system.mem_ctrl.rdQLenPdf::14 0
|
||||
system.mem_ctrl.rdQLenPdf::15 0
|
||||
system.mem_ctrl.rdQLenPdf::16 0
|
||||
system.mem_ctrl.rdQLenPdf::17 0
|
||||
system.mem_ctrl.rdQLenPdf::18 0
|
||||
system.mem_ctrl.rdQLenPdf::19 0
|
||||
system.mem_ctrl.rdQLenPdf::20 0
|
||||
system.mem_ctrl.rdQLenPdf::21 0
|
||||
system.mem_ctrl.rdQLenPdf::22 0
|
||||
system.mem_ctrl.rdQLenPdf::23 0
|
||||
system.mem_ctrl.rdQLenPdf::24 0
|
||||
system.mem_ctrl.rdQLenPdf::25 0
|
||||
system.mem_ctrl.rdQLenPdf::26 0
|
||||
system.mem_ctrl.rdQLenPdf::27 0
|
||||
system.mem_ctrl.rdQLenPdf::28 0
|
||||
system.mem_ctrl.rdQLenPdf::29 0
|
||||
system.mem_ctrl.rdQLenPdf::30 0
|
||||
system.mem_ctrl.rdQLenPdf::31 0
|
||||
system.mem_ctrl.wrQLenPdf::0 1
|
||||
system.mem_ctrl.wrQLenPdf::1 1
|
||||
system.mem_ctrl.wrQLenPdf::2 1
|
||||
system.mem_ctrl.wrQLenPdf::3 1
|
||||
system.mem_ctrl.wrQLenPdf::4 1
|
||||
system.mem_ctrl.wrQLenPdf::5 1
|
||||
system.mem_ctrl.wrQLenPdf::6 1
|
||||
system.mem_ctrl.wrQLenPdf::7 1
|
||||
system.mem_ctrl.wrQLenPdf::8 1
|
||||
system.mem_ctrl.wrQLenPdf::9 1
|
||||
system.mem_ctrl.wrQLenPdf::10 1
|
||||
system.mem_ctrl.wrQLenPdf::11 1
|
||||
system.mem_ctrl.wrQLenPdf::12 1
|
||||
system.mem_ctrl.wrQLenPdf::13 1
|
||||
system.mem_ctrl.wrQLenPdf::14 1
|
||||
system.mem_ctrl.wrQLenPdf::15 1
|
||||
system.mem_ctrl.wrQLenPdf::16 1
|
||||
system.mem_ctrl.wrQLenPdf::17 4
|
||||
system.mem_ctrl.wrQLenPdf::18 4
|
||||
system.mem_ctrl.wrQLenPdf::19 4
|
||||
system.mem_ctrl.wrQLenPdf::20 4
|
||||
system.mem_ctrl.wrQLenPdf::21 4
|
||||
system.mem_ctrl.wrQLenPdf::22 4
|
||||
system.mem_ctrl.wrQLenPdf::23 4
|
||||
system.mem_ctrl.wrQLenPdf::24 4
|
||||
system.mem_ctrl.wrQLenPdf::25 4
|
||||
system.mem_ctrl.wrQLenPdf::26 4
|
||||
system.mem_ctrl.wrQLenPdf::27 4
|
||||
system.mem_ctrl.wrQLenPdf::28 4
|
||||
system.mem_ctrl.wrQLenPdf::29 4
|
||||
system.mem_ctrl.wrQLenPdf::30 4
|
||||
system.mem_ctrl.wrQLenPdf::31 4
|
||||
system.mem_ctrl.wrQLenPdf::32 4
|
||||
system.mem_ctrl.wrQLenPdf::33 0
|
||||
system.mem_ctrl.wrQLenPdf::34 0
|
||||
system.mem_ctrl.wrQLenPdf::35 0
|
||||
system.mem_ctrl.wrQLenPdf::36 0
|
||||
system.mem_ctrl.wrQLenPdf::37 0
|
||||
system.mem_ctrl.wrQLenPdf::38 0
|
||||
system.mem_ctrl.wrQLenPdf::39 0
|
||||
system.mem_ctrl.wrQLenPdf::40 0
|
||||
system.mem_ctrl.wrQLenPdf::41 0
|
||||
system.mem_ctrl.wrQLenPdf::42 0
|
||||
system.mem_ctrl.wrQLenPdf::43 0
|
||||
system.mem_ctrl.wrQLenPdf::44 0
|
||||
system.mem_ctrl.wrQLenPdf::45 0
|
||||
system.mem_ctrl.wrQLenPdf::46 0
|
||||
system.mem_ctrl.wrQLenPdf::47 0
|
||||
system.mem_ctrl.wrQLenPdf::48 0
|
||||
system.mem_ctrl.wrQLenPdf::49 0
|
||||
system.mem_ctrl.wrQLenPdf::50 0
|
||||
system.mem_ctrl.wrQLenPdf::51 0
|
||||
system.mem_ctrl.wrQLenPdf::52 0
|
||||
system.mem_ctrl.wrQLenPdf::53 0
|
||||
system.mem_ctrl.wrQLenPdf::54 0
|
||||
system.mem_ctrl.wrQLenPdf::55 0
|
||||
system.mem_ctrl.wrQLenPdf::56 0
|
||||
system.mem_ctrl.wrQLenPdf::57 0
|
||||
system.mem_ctrl.wrQLenPdf::58 0
|
||||
system.mem_ctrl.wrQLenPdf::59 0
|
||||
system.mem_ctrl.wrQLenPdf::60 0
|
||||
system.mem_ctrl.wrQLenPdf::61 0
|
||||
system.mem_ctrl.wrQLenPdf::62 0
|
||||
system.mem_ctrl.wrQLenPdf::63 0
|
||||
system.mem_ctrl.bytesPerActivate::samples 514
|
||||
system.mem_ctrl.bytesPerActivate::mean 749.322957
|
||||
system.mem_ctrl.bytesPerActivate::gmean 608.037375
|
||||
system.mem_ctrl.bytesPerActivate::stdev 344.826867
|
||||
system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86%
|
||||
system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04%
|
||||
system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60%
|
||||
system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65%
|
||||
system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52%
|
||||
system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13%
|
||||
system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39%
|
||||
system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64%
|
||||
system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00%
|
||||
system.mem_ctrl.bytesPerActivate::total 514
|
||||
system.mem_ctrl.rdPerTurnAround::samples 4
|
||||
system.mem_ctrl.rdPerTurnAround::mean 1490.500000
|
||||
system.mem_ctrl.rdPerTurnAround::gmean 1373.591360
|
||||
system.mem_ctrl.rdPerTurnAround::stdev 606.712727
|
||||
system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00%
|
||||
system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00%
|
||||
system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00%
|
||||
system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00%
|
||||
system.mem_ctrl.rdPerTurnAround::total 4
|
||||
system.mem_ctrl.wrPerTurnAround::samples 4
|
||||
system.mem_ctrl.wrPerTurnAround::mean 16
|
||||
system.mem_ctrl.wrPerTurnAround::gmean 16.000000
|
||||
system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00%
|
||||
system.mem_ctrl.wrPerTurnAround::total 4
|
||||
system.mem_ctrl.totQLat 57609500
|
||||
system.mem_ctrl.totMemAccLat 169903250
|
||||
system.mem_ctrl.totBusLat 29945000
|
||||
system.mem_ctrl.avgQLat 9619.22
|
||||
system.mem_ctrl.avgBusLat 5000.00
|
||||
system.mem_ctrl.avgMemAccLat 28369.22
|
||||
system.mem_ctrl.avgRdBW 1029.58
|
||||
system.mem_ctrl.avgWrBW 11.00
|
||||
system.mem_ctrl.avgRdBWSys 66.57
|
||||
system.mem_ctrl.avgWrBWSys 9.93
|
||||
system.mem_ctrl.peakBW 12800.00
|
||||
system.mem_ctrl.busUtil 8.13
|
||||
system.mem_ctrl.busUtilRead 8.04
|
||||
system.mem_ctrl.busUtilWrite 0.09
|
||||
system.mem_ctrl.avgRdQLen 1.00
|
||||
system.mem_ctrl.avgWrQLen 24.94
|
||||
system.mem_ctrl.readRowHits 5473
|
||||
system.mem_ctrl.writeRowHits 62
|
||||
system.mem_ctrl.readRowHitRate 91.38
|
||||
system.mem_ctrl.writeRowHitRate 76.54
|
||||
system.mem_ctrl.avgGap 52983.20
|
||||
system.mem_ctrl.pageHitRate 91.19
|
||||
system.mem_ctrl_0.actEnergy 2727480
|
||||
system.mem_ctrl_0.preEnergy 1438305
|
||||
system.mem_ctrl_0.readEnergy 35364420
|
||||
system.mem_ctrl_0.writeEnergy 0
|
||||
system.mem_ctrl_0.refreshEnergy 28888080.000000
|
||||
system.mem_ctrl_0.actBackEnergy 64999380
|
||||
system.mem_ctrl_0.preBackEnergy 1619520
|
||||
system.mem_ctrl_0.actPowerDownEnergy 98643060
|
||||
system.mem_ctrl_0.prePowerDownEnergy 3533760
|
||||
system.mem_ctrl_0.selfRefreshEnergy 0
|
||||
system.mem_ctrl_0.totalEnergy 237214005
|
||||
system.mem_ctrl_0.averagePower 637.183891
|
||||
system.mem_ctrl_0.totalIdleTime 225396250
|
||||
system.mem_ctrl_0.memoryStateTime::IDLE 954000
|
||||
system.mem_ctrl_0.memoryStateTime::REF 12220000
|
||||
system.mem_ctrl_0.memoryStateTime::SREF 0
|
||||
system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500
|
||||
system.mem_ctrl_0.memoryStateTime::ACT 133713750
|
||||
system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750
|
||||
system.mem_ctrl_1.actEnergy 971040
|
||||
system.mem_ctrl_1.preEnergy 512325
|
||||
system.mem_ctrl_1.readEnergy 7389900
|
||||
system.mem_ctrl_1.writeEnergy 334080
|
||||
system.mem_ctrl_1.refreshEnergy 27658800.000000
|
||||
system.mem_ctrl_1.actBackEnergy 18607080
|
||||
system.mem_ctrl_1.preBackEnergy 791520
|
||||
system.mem_ctrl_1.actPowerDownEnergy 128152530
|
||||
system.mem_ctrl_1.prePowerDownEnergy 7837920
|
||||
system.mem_ctrl_1.selfRefreshEnergy 7265340
|
||||
system.mem_ctrl_1.totalEnergy 199520535
|
||||
system.mem_ctrl_1.averagePower 535.934929
|
||||
system.mem_ctrl_1.totalIdleTime 328663750
|
||||
system.mem_ctrl_1.memoryStateTime::IDLE 770000
|
||||
system.mem_ctrl_1.memoryStateTime::REF 11706000
|
||||
system.mem_ctrl_1.memoryStateTime::SREF 27971000
|
||||
system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250
|
||||
system.mem_ctrl_1.memoryStateTime::ACT 30385000
|
||||
system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750
|
||||
system.pwrStateResidencyTicks::UNDEFINED 372284000
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 372284000
|
||||
system.cpu.dtb.walker.walks 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dtb.inst_hits 0
|
||||
system.cpu.dtb.inst_misses 0
|
||||
system.cpu.dtb.read_hits 0
|
||||
system.cpu.dtb.read_misses 0
|
||||
system.cpu.dtb.write_hits 0
|
||||
system.cpu.dtb.write_misses 0
|
||||
system.cpu.dtb.flush_tlb 0
|
||||
system.cpu.dtb.flush_tlb_mva 0
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0
|
||||
system.cpu.dtb.flush_tlb_asid 0
|
||||
system.cpu.dtb.flush_entries 0
|
||||
system.cpu.dtb.align_faults 0
|
||||
system.cpu.dtb.prefetch_faults 0
|
||||
system.cpu.dtb.domain_faults 0
|
||||
system.cpu.dtb.perms_faults 0
|
||||
system.cpu.dtb.read_accesses 0
|
||||
system.cpu.dtb.write_accesses 0
|
||||
system.cpu.dtb.inst_accesses 0
|
||||
system.cpu.dtb.hits 0
|
||||
system.cpu.dtb.misses 0
|
||||
system.cpu.dtb.accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000
|
||||
system.cpu.itb.walker.walks 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.itb.inst_hits 0
|
||||
system.cpu.itb.inst_misses 0
|
||||
system.cpu.itb.read_hits 0
|
||||
system.cpu.itb.read_misses 0
|
||||
system.cpu.itb.write_hits 0
|
||||
system.cpu.itb.write_misses 0
|
||||
system.cpu.itb.flush_tlb 0
|
||||
system.cpu.itb.flush_tlb_mva 0
|
||||
system.cpu.itb.flush_tlb_mva_asid 0
|
||||
system.cpu.itb.flush_tlb_asid 0
|
||||
system.cpu.itb.flush_entries 0
|
||||
system.cpu.itb.align_faults 0
|
||||
system.cpu.itb.prefetch_faults 0
|
||||
system.cpu.itb.domain_faults 0
|
||||
system.cpu.itb.perms_faults 0
|
||||
system.cpu.itb.read_accesses 0
|
||||
system.cpu.itb.write_accesses 0
|
||||
system.cpu.itb.inst_accesses 0
|
||||
system.cpu.itb.hits 0
|
||||
system.cpu.itb.misses 0
|
||||
system.cpu.itb.accesses 0
|
||||
system.cpu.workload.numSyscalls 13
|
||||
system.cpu.pwrStateResidencyTicks::ON 372284000
|
||||
system.cpu.numCycles 372284
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 4988
|
||||
system.cpu.committedOps 5770
|
||||
system.cpu.num_int_alu_accesses 4977
|
||||
system.cpu.num_fp_alu_accesses 16
|
||||
system.cpu.num_func_calls 215
|
||||
system.cpu.num_conditional_control_insts 800
|
||||
system.cpu.num_int_insts 4977
|
||||
system.cpu.num_fp_insts 16
|
||||
system.cpu.num_int_register_reads 8049
|
||||
system.cpu.num_int_register_writes 2992
|
||||
system.cpu.num_fp_register_reads 16
|
||||
system.cpu.num_fp_register_writes 0
|
||||
system.cpu.num_cc_register_reads 20681
|
||||
system.cpu.num_cc_register_writes 2647
|
||||
system.cpu.num_mem_refs 2035
|
||||
system.cpu.num_load_insts 1085
|
||||
system.cpu.num_store_insts 950
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 372284
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 1107
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00%
|
||||
system.cpu.op_class::IntAlu 3789 64.98% 64.98%
|
||||
system.cpu.op_class::IntMult 4 0.07% 65.05%
|
||||
system.cpu.op_class::IntDiv 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.10%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10%
|
||||
system.cpu.op_class::MemRead 1085 18.61% 83.71%
|
||||
system.cpu.op_class::MemWrite 934 16.02% 99.73%
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 99.73%
|
||||
system.cpu.op_class::FloatMemWrite 16 0.27% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 5831
|
||||
system.membus.snoop_filter.tot_requests 0
|
||||
system.membus.snoop_filter.hit_single_requests 0
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 372284000
|
||||
system.membus.trans_dist::ReadReq 6078
|
||||
system.membus.trans_dist::ReadResp 6088
|
||||
system.membus.trans_dist::WriteReq 925
|
||||
system.membus.trans_dist::WriteResp 925
|
||||
system.membus.trans_dist::LoadLockedReq 11
|
||||
system.membus.trans_dist::StoreCondReq 11
|
||||
system.membus.trans_dist::StoreCondResp 11
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994
|
||||
system.membus.pkt_count::total 14049
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368
|
||||
system.membus.pkt_size::total 28476
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 7025
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 7025 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 7025
|
||||
system.membus.reqLayer0.occupancy 7961000
|
||||
system.membus.reqLayer0.utilization 2.1
|
||||
system.membus.respLayer0.occupancy 11413250
|
||||
system.membus.respLayer0.utilization 3.1
|
||||
system.membus.respLayer1.occupancy 3327250
|
||||
system.membus.respLayer1.utilization 0.9
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,554 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.mem_ctrl
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[1]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
children=voltage_domain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.clk_domain.voltage_domain
|
||||
|
||||
[system.clk_domain.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=-1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=65536
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.l2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=65536
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=16384
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.l2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=16384
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=tests/test-progs/hello/bin/arm/linux/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.l2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.l2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.l2bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=262144
|
||||
tag_latency=20
|
||||
|
||||
[system.mem_ctrl]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:536870911:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.mem_ctrl.port
|
||||
slave=system.l2cache.mem_side system.system_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
@@ -1,14 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 17:55:48
|
||||
gem5 started Apr 3 2017 18:08:19
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55755
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Beginning simulation!
|
||||
Hello world!
|
||||
Exiting @ tick 52453000 because exiting with last active thread context
|
||||
@@ -1,846 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000052
|
||||
sim_ticks 52453000
|
||||
final_tick 52453000
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 255460
|
||||
host_op_rate 295178
|
||||
host_tick_rate 2680706051
|
||||
host_mem_usage 666596
|
||||
host_seconds 0.02
|
||||
sim_insts 4988
|
||||
sim_ops 5770
|
||||
system.clk_domain.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.mem_ctrl.bytes_read::cpu.inst 14400
|
||||
system.mem_ctrl.bytes_read::cpu.data 8064
|
||||
system.mem_ctrl.bytes_read::total 22464
|
||||
system.mem_ctrl.bytes_inst_read::cpu.inst 14400
|
||||
system.mem_ctrl.bytes_inst_read::total 14400
|
||||
system.mem_ctrl.num_reads::cpu.inst 225
|
||||
system.mem_ctrl.num_reads::cpu.data 126
|
||||
system.mem_ctrl.num_reads::total 351
|
||||
system.mem_ctrl.bw_read::cpu.inst 274531485
|
||||
system.mem_ctrl.bw_read::cpu.data 153737632
|
||||
system.mem_ctrl.bw_read::total 428269117
|
||||
system.mem_ctrl.bw_inst_read::cpu.inst 274531485
|
||||
system.mem_ctrl.bw_inst_read::total 274531485
|
||||
system.mem_ctrl.bw_total::cpu.inst 274531485
|
||||
system.mem_ctrl.bw_total::cpu.data 153737632
|
||||
system.mem_ctrl.bw_total::total 428269117
|
||||
system.mem_ctrl.readReqs 351
|
||||
system.mem_ctrl.writeReqs 0
|
||||
system.mem_ctrl.readBursts 351
|
||||
system.mem_ctrl.writeBursts 0
|
||||
system.mem_ctrl.bytesReadDRAM 22464
|
||||
system.mem_ctrl.bytesReadWrQ 0
|
||||
system.mem_ctrl.bytesWritten 0
|
||||
system.mem_ctrl.bytesReadSys 22464
|
||||
system.mem_ctrl.bytesWrittenSys 0
|
||||
system.mem_ctrl.servicedByWrQ 0
|
||||
system.mem_ctrl.mergedWrBursts 0
|
||||
system.mem_ctrl.neitherReadNorWriteReqs 0
|
||||
system.mem_ctrl.perBankRdBursts::0 78
|
||||
system.mem_ctrl.perBankRdBursts::1 42
|
||||
system.mem_ctrl.perBankRdBursts::2 13
|
||||
system.mem_ctrl.perBankRdBursts::3 33
|
||||
system.mem_ctrl.perBankRdBursts::4 14
|
||||
system.mem_ctrl.perBankRdBursts::5 31
|
||||
system.mem_ctrl.perBankRdBursts::6 34
|
||||
system.mem_ctrl.perBankRdBursts::7 9
|
||||
system.mem_ctrl.perBankRdBursts::8 4
|
||||
system.mem_ctrl.perBankRdBursts::9 6
|
||||
system.mem_ctrl.perBankRdBursts::10 25
|
||||
system.mem_ctrl.perBankRdBursts::11 43
|
||||
system.mem_ctrl.perBankRdBursts::12 8
|
||||
system.mem_ctrl.perBankRdBursts::13 5
|
||||
system.mem_ctrl.perBankRdBursts::14 0
|
||||
system.mem_ctrl.perBankRdBursts::15 6
|
||||
system.mem_ctrl.perBankWrBursts::0 0
|
||||
system.mem_ctrl.perBankWrBursts::1 0
|
||||
system.mem_ctrl.perBankWrBursts::2 0
|
||||
system.mem_ctrl.perBankWrBursts::3 0
|
||||
system.mem_ctrl.perBankWrBursts::4 0
|
||||
system.mem_ctrl.perBankWrBursts::5 0
|
||||
system.mem_ctrl.perBankWrBursts::6 0
|
||||
system.mem_ctrl.perBankWrBursts::7 0
|
||||
system.mem_ctrl.perBankWrBursts::8 0
|
||||
system.mem_ctrl.perBankWrBursts::9 0
|
||||
system.mem_ctrl.perBankWrBursts::10 0
|
||||
system.mem_ctrl.perBankWrBursts::11 0
|
||||
system.mem_ctrl.perBankWrBursts::12 0
|
||||
system.mem_ctrl.perBankWrBursts::13 0
|
||||
system.mem_ctrl.perBankWrBursts::14 0
|
||||
system.mem_ctrl.perBankWrBursts::15 0
|
||||
system.mem_ctrl.numRdRetry 0
|
||||
system.mem_ctrl.numWrRetry 0
|
||||
system.mem_ctrl.totGap 52348000
|
||||
system.mem_ctrl.readPktSize::0 0
|
||||
system.mem_ctrl.readPktSize::1 0
|
||||
system.mem_ctrl.readPktSize::2 0
|
||||
system.mem_ctrl.readPktSize::3 0
|
||||
system.mem_ctrl.readPktSize::4 0
|
||||
system.mem_ctrl.readPktSize::5 0
|
||||
system.mem_ctrl.readPktSize::6 351
|
||||
system.mem_ctrl.writePktSize::0 0
|
||||
system.mem_ctrl.writePktSize::1 0
|
||||
system.mem_ctrl.writePktSize::2 0
|
||||
system.mem_ctrl.writePktSize::3 0
|
||||
system.mem_ctrl.writePktSize::4 0
|
||||
system.mem_ctrl.writePktSize::5 0
|
||||
system.mem_ctrl.writePktSize::6 0
|
||||
system.mem_ctrl.rdQLenPdf::0 351
|
||||
system.mem_ctrl.rdQLenPdf::1 0
|
||||
system.mem_ctrl.rdQLenPdf::2 0
|
||||
system.mem_ctrl.rdQLenPdf::3 0
|
||||
system.mem_ctrl.rdQLenPdf::4 0
|
||||
system.mem_ctrl.rdQLenPdf::5 0
|
||||
system.mem_ctrl.rdQLenPdf::6 0
|
||||
system.mem_ctrl.rdQLenPdf::7 0
|
||||
system.mem_ctrl.rdQLenPdf::8 0
|
||||
system.mem_ctrl.rdQLenPdf::9 0
|
||||
system.mem_ctrl.rdQLenPdf::10 0
|
||||
system.mem_ctrl.rdQLenPdf::11 0
|
||||
system.mem_ctrl.rdQLenPdf::12 0
|
||||
system.mem_ctrl.rdQLenPdf::13 0
|
||||
system.mem_ctrl.rdQLenPdf::14 0
|
||||
system.mem_ctrl.rdQLenPdf::15 0
|
||||
system.mem_ctrl.rdQLenPdf::16 0
|
||||
system.mem_ctrl.rdQLenPdf::17 0
|
||||
system.mem_ctrl.rdQLenPdf::18 0
|
||||
system.mem_ctrl.rdQLenPdf::19 0
|
||||
system.mem_ctrl.rdQLenPdf::20 0
|
||||
system.mem_ctrl.rdQLenPdf::21 0
|
||||
system.mem_ctrl.rdQLenPdf::22 0
|
||||
system.mem_ctrl.rdQLenPdf::23 0
|
||||
system.mem_ctrl.rdQLenPdf::24 0
|
||||
system.mem_ctrl.rdQLenPdf::25 0
|
||||
system.mem_ctrl.rdQLenPdf::26 0
|
||||
system.mem_ctrl.rdQLenPdf::27 0
|
||||
system.mem_ctrl.rdQLenPdf::28 0
|
||||
system.mem_ctrl.rdQLenPdf::29 0
|
||||
system.mem_ctrl.rdQLenPdf::30 0
|
||||
system.mem_ctrl.rdQLenPdf::31 0
|
||||
system.mem_ctrl.wrQLenPdf::0 0
|
||||
system.mem_ctrl.wrQLenPdf::1 0
|
||||
system.mem_ctrl.wrQLenPdf::2 0
|
||||
system.mem_ctrl.wrQLenPdf::3 0
|
||||
system.mem_ctrl.wrQLenPdf::4 0
|
||||
system.mem_ctrl.wrQLenPdf::5 0
|
||||
system.mem_ctrl.wrQLenPdf::6 0
|
||||
system.mem_ctrl.wrQLenPdf::7 0
|
||||
system.mem_ctrl.wrQLenPdf::8 0
|
||||
system.mem_ctrl.wrQLenPdf::9 0
|
||||
system.mem_ctrl.wrQLenPdf::10 0
|
||||
system.mem_ctrl.wrQLenPdf::11 0
|
||||
system.mem_ctrl.wrQLenPdf::12 0
|
||||
system.mem_ctrl.wrQLenPdf::13 0
|
||||
system.mem_ctrl.wrQLenPdf::14 0
|
||||
system.mem_ctrl.wrQLenPdf::15 0
|
||||
system.mem_ctrl.wrQLenPdf::16 0
|
||||
system.mem_ctrl.wrQLenPdf::17 0
|
||||
system.mem_ctrl.wrQLenPdf::18 0
|
||||
system.mem_ctrl.wrQLenPdf::19 0
|
||||
system.mem_ctrl.wrQLenPdf::20 0
|
||||
system.mem_ctrl.wrQLenPdf::21 0
|
||||
system.mem_ctrl.wrQLenPdf::22 0
|
||||
system.mem_ctrl.wrQLenPdf::23 0
|
||||
system.mem_ctrl.wrQLenPdf::24 0
|
||||
system.mem_ctrl.wrQLenPdf::25 0
|
||||
system.mem_ctrl.wrQLenPdf::26 0
|
||||
system.mem_ctrl.wrQLenPdf::27 0
|
||||
system.mem_ctrl.wrQLenPdf::28 0
|
||||
system.mem_ctrl.wrQLenPdf::29 0
|
||||
system.mem_ctrl.wrQLenPdf::30 0
|
||||
system.mem_ctrl.wrQLenPdf::31 0
|
||||
system.mem_ctrl.wrQLenPdf::32 0
|
||||
system.mem_ctrl.wrQLenPdf::33 0
|
||||
system.mem_ctrl.wrQLenPdf::34 0
|
||||
system.mem_ctrl.wrQLenPdf::35 0
|
||||
system.mem_ctrl.wrQLenPdf::36 0
|
||||
system.mem_ctrl.wrQLenPdf::37 0
|
||||
system.mem_ctrl.wrQLenPdf::38 0
|
||||
system.mem_ctrl.wrQLenPdf::39 0
|
||||
system.mem_ctrl.wrQLenPdf::40 0
|
||||
system.mem_ctrl.wrQLenPdf::41 0
|
||||
system.mem_ctrl.wrQLenPdf::42 0
|
||||
system.mem_ctrl.wrQLenPdf::43 0
|
||||
system.mem_ctrl.wrQLenPdf::44 0
|
||||
system.mem_ctrl.wrQLenPdf::45 0
|
||||
system.mem_ctrl.wrQLenPdf::46 0
|
||||
system.mem_ctrl.wrQLenPdf::47 0
|
||||
system.mem_ctrl.wrQLenPdf::48 0
|
||||
system.mem_ctrl.wrQLenPdf::49 0
|
||||
system.mem_ctrl.wrQLenPdf::50 0
|
||||
system.mem_ctrl.wrQLenPdf::51 0
|
||||
system.mem_ctrl.wrQLenPdf::52 0
|
||||
system.mem_ctrl.wrQLenPdf::53 0
|
||||
system.mem_ctrl.wrQLenPdf::54 0
|
||||
system.mem_ctrl.wrQLenPdf::55 0
|
||||
system.mem_ctrl.wrQLenPdf::56 0
|
||||
system.mem_ctrl.wrQLenPdf::57 0
|
||||
system.mem_ctrl.wrQLenPdf::58 0
|
||||
system.mem_ctrl.wrQLenPdf::59 0
|
||||
system.mem_ctrl.wrQLenPdf::60 0
|
||||
system.mem_ctrl.wrQLenPdf::61 0
|
||||
system.mem_ctrl.wrQLenPdf::62 0
|
||||
system.mem_ctrl.wrQLenPdf::63 0
|
||||
system.mem_ctrl.bytesPerActivate::samples 75
|
||||
system.mem_ctrl.bytesPerActivate::mean 285.866667
|
||||
system.mem_ctrl.bytesPerActivate::gmean 188.503913
|
||||
system.mem_ctrl.bytesPerActivate::stdev 282.583704
|
||||
system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33%
|
||||
system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00%
|
||||
system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00%
|
||||
system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33%
|
||||
system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67%
|
||||
system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33%
|
||||
system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00%
|
||||
system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00%
|
||||
system.mem_ctrl.bytesPerActivate::total 75
|
||||
system.mem_ctrl.totQLat 4720500
|
||||
system.mem_ctrl.totMemAccLat 11301750
|
||||
system.mem_ctrl.totBusLat 1755000
|
||||
system.mem_ctrl.avgQLat 13448.72
|
||||
system.mem_ctrl.avgBusLat 5000.00
|
||||
system.mem_ctrl.avgMemAccLat 32198.72
|
||||
system.mem_ctrl.avgRdBW 428.27
|
||||
system.mem_ctrl.avgWrBW 0.00
|
||||
system.mem_ctrl.avgRdBWSys 428.27
|
||||
system.mem_ctrl.avgWrBWSys 0.00
|
||||
system.mem_ctrl.peakBW 12800.00
|
||||
system.mem_ctrl.busUtil 3.35
|
||||
system.mem_ctrl.busUtilRead 3.35
|
||||
system.mem_ctrl.busUtilWrite 0.00
|
||||
system.mem_ctrl.avgRdQLen 1.00
|
||||
system.mem_ctrl.avgWrQLen 0.00
|
||||
system.mem_ctrl.readRowHits 270
|
||||
system.mem_ctrl.writeRowHits 0
|
||||
system.mem_ctrl.readRowHitRate 76.92
|
||||
system.mem_ctrl.writeRowHitRate nan
|
||||
system.mem_ctrl.avgGap 149139.60
|
||||
system.mem_ctrl.pageHitRate 76.92
|
||||
system.mem_ctrl_0.actEnergy 378420
|
||||
system.mem_ctrl_0.preEnergy 189750
|
||||
system.mem_ctrl_0.readEnergy 1813560
|
||||
system.mem_ctrl_0.writeEnergy 0
|
||||
system.mem_ctrl_0.refreshEnergy 3687840.000000
|
||||
system.mem_ctrl_0.actBackEnergy 4500720
|
||||
system.mem_ctrl_0.preBackEnergy 84480
|
||||
system.mem_ctrl_0.actPowerDownEnergy 19212990
|
||||
system.mem_ctrl_0.prePowerDownEnergy 88320
|
||||
system.mem_ctrl_0.selfRefreshEnergy 0
|
||||
system.mem_ctrl_0.totalEnergy 29956080
|
||||
system.mem_ctrl_0.averagePower 571.095108
|
||||
system.mem_ctrl_0.totalIdleTime 42304000
|
||||
system.mem_ctrl_0.memoryStateTime::IDLE 53000
|
||||
system.mem_ctrl_0.memoryStateTime::REF 1560000
|
||||
system.mem_ctrl_0.memoryStateTime::SREF 0
|
||||
system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750
|
||||
system.mem_ctrl_0.memoryStateTime::ACT 8478750
|
||||
system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500
|
||||
system.mem_ctrl_1.actEnergy 199920
|
||||
system.mem_ctrl_1.preEnergy 94875
|
||||
system.mem_ctrl_1.readEnergy 692580
|
||||
system.mem_ctrl_1.writeEnergy 0
|
||||
system.mem_ctrl_1.refreshEnergy 3687840.000000
|
||||
system.mem_ctrl_1.actBackEnergy 2032620
|
||||
system.mem_ctrl_1.preBackEnergy 139680
|
||||
system.mem_ctrl_1.actPowerDownEnergy 19936320
|
||||
system.mem_ctrl_1.prePowerDownEnergy 1502400
|
||||
system.mem_ctrl_1.selfRefreshEnergy 0
|
||||
system.mem_ctrl_1.totalEnergy 28286235
|
||||
system.mem_ctrl_1.averagePower 539.260491
|
||||
system.mem_ctrl_1.totalIdleTime 44784500
|
||||
system.mem_ctrl_1.memoryStateTime::IDLE 200000
|
||||
system.mem_ctrl_1.memoryStateTime::REF 1560000
|
||||
system.mem_ctrl_1.memoryStateTime::SREF 0
|
||||
system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750
|
||||
system.mem_ctrl_1.memoryStateTime::ACT 3056250
|
||||
system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000
|
||||
system.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.cpu.dtb.walker.walks 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dtb.inst_hits 0
|
||||
system.cpu.dtb.inst_misses 0
|
||||
system.cpu.dtb.read_hits 0
|
||||
system.cpu.dtb.read_misses 0
|
||||
system.cpu.dtb.write_hits 0
|
||||
system.cpu.dtb.write_misses 0
|
||||
system.cpu.dtb.flush_tlb 0
|
||||
system.cpu.dtb.flush_tlb_mva 0
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0
|
||||
system.cpu.dtb.flush_tlb_asid 0
|
||||
system.cpu.dtb.flush_entries 0
|
||||
system.cpu.dtb.align_faults 0
|
||||
system.cpu.dtb.prefetch_faults 0
|
||||
system.cpu.dtb.domain_faults 0
|
||||
system.cpu.dtb.perms_faults 0
|
||||
system.cpu.dtb.read_accesses 0
|
||||
system.cpu.dtb.write_accesses 0
|
||||
system.cpu.dtb.inst_accesses 0
|
||||
system.cpu.dtb.hits 0
|
||||
system.cpu.dtb.misses 0
|
||||
system.cpu.dtb.accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.cpu.itb.walker.walks 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.itb.inst_hits 0
|
||||
system.cpu.itb.inst_misses 0
|
||||
system.cpu.itb.read_hits 0
|
||||
system.cpu.itb.read_misses 0
|
||||
system.cpu.itb.write_hits 0
|
||||
system.cpu.itb.write_misses 0
|
||||
system.cpu.itb.flush_tlb 0
|
||||
system.cpu.itb.flush_tlb_mva 0
|
||||
system.cpu.itb.flush_tlb_mva_asid 0
|
||||
system.cpu.itb.flush_tlb_asid 0
|
||||
system.cpu.itb.flush_entries 0
|
||||
system.cpu.itb.align_faults 0
|
||||
system.cpu.itb.prefetch_faults 0
|
||||
system.cpu.itb.domain_faults 0
|
||||
system.cpu.itb.perms_faults 0
|
||||
system.cpu.itb.read_accesses 0
|
||||
system.cpu.itb.write_accesses 0
|
||||
system.cpu.itb.inst_accesses 0
|
||||
system.cpu.itb.hits 0
|
||||
system.cpu.itb.misses 0
|
||||
system.cpu.itb.accesses 0
|
||||
system.cpu.workload.numSyscalls 13
|
||||
system.cpu.pwrStateResidencyTicks::ON 52453000
|
||||
system.cpu.numCycles 52453
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 4988
|
||||
system.cpu.committedOps 5770
|
||||
system.cpu.num_int_alu_accesses 4977
|
||||
system.cpu.num_fp_alu_accesses 16
|
||||
system.cpu.num_func_calls 215
|
||||
system.cpu.num_conditional_control_insts 800
|
||||
system.cpu.num_int_insts 4977
|
||||
system.cpu.num_fp_insts 16
|
||||
system.cpu.num_int_register_reads 8049
|
||||
system.cpu.num_int_register_writes 2992
|
||||
system.cpu.num_fp_register_reads 16
|
||||
system.cpu.num_fp_register_writes 0
|
||||
system.cpu.num_cc_register_reads 20681
|
||||
system.cpu.num_cc_register_writes 2647
|
||||
system.cpu.num_mem_refs 2035
|
||||
system.cpu.num_load_insts 1085
|
||||
system.cpu.num_store_insts 950
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 52453
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 1107
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00%
|
||||
system.cpu.op_class::IntAlu 3789 64.98% 64.98%
|
||||
system.cpu.op_class::IntMult 4 0.07% 65.05%
|
||||
system.cpu.op_class::IntDiv 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 65.05%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05%
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.10%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10%
|
||||
system.cpu.op_class::MemRead 1085 18.61% 83.71%
|
||||
system.cpu.op_class::MemWrite 934 16.02% 99.73%
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 99.73%
|
||||
system.cpu.op_class::FloatMemWrite 16 0.27% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 5831
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.cpu.dcache.tags.replacements 0
|
||||
system.cpu.dcache.tags.tagsinuse 84.380856
|
||||
system.cpu.dcache.tags.total_refs 1855
|
||||
system.cpu.dcache.tags.sampled_refs 142
|
||||
system.cpu.dcache.tags.avg_refs 13.063380
|
||||
system.cpu.dcache.tags.warmup_cycle 0
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 84.380856
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.082403
|
||||
system.cpu.dcache.tags.occ_percent::total 0.082403
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 142
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 123
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672
|
||||
system.cpu.dcache.tags.tag_accesses 4136
|
||||
system.cpu.dcache.tags.data_accesses 4136
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 951
|
||||
system.cpu.dcache.ReadReq_hits::total 951
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 882
|
||||
system.cpu.dcache.WriteReq_hits::total 882
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 11
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 11
|
||||
system.cpu.dcache.StoreCondReq_hits::total 11
|
||||
system.cpu.dcache.demand_hits::cpu.data 1833
|
||||
system.cpu.dcache.demand_hits::total 1833
|
||||
system.cpu.dcache.overall_hits::cpu.data 1833
|
||||
system.cpu.dcache.overall_hits::total 1833
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 99
|
||||
system.cpu.dcache.ReadReq_misses::total 99
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 43
|
||||
system.cpu.dcache.WriteReq_misses::total 43
|
||||
system.cpu.dcache.demand_misses::cpu.data 142
|
||||
system.cpu.dcache.demand_misses::total 142
|
||||
system.cpu.dcache.overall_misses::cpu.data 142
|
||||
system.cpu.dcache.overall_misses::total 142
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9073000
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 9073000
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4652000
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4652000
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13725000
|
||||
system.cpu.dcache.demand_miss_latency::total 13725000
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13725000
|
||||
system.cpu.dcache.overall_miss_latency::total 13725000
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1050
|
||||
system.cpu.dcache.ReadReq_accesses::total 1050
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 925
|
||||
system.cpu.dcache.WriteReq_accesses::total 925
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 11
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 11
|
||||
system.cpu.dcache.demand_accesses::cpu.data 1975
|
||||
system.cpu.dcache.demand_accesses::total 1975
|
||||
system.cpu.dcache.overall_accesses::cpu.data 1975
|
||||
system.cpu.dcache.overall_accesses::total 1975
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.094286
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.046486
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.071899
|
||||
system.cpu.dcache.demand_miss_rate::total 0.071899
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.071899
|
||||
system.cpu.dcache.overall_miss_rate::total 0.071899
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 96654.929577
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 96654.929577
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0
|
||||
system.cpu.dcache.blocked::no_mshrs 0
|
||||
system.cpu.dcache.blocked::no_targets 0
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 99
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 43
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 142
|
||||
system.cpu.dcache.demand_mshr_misses::total 142
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 142
|
||||
system.cpu.dcache.overall_mshr_misses::total 142
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8875000
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 8875000
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4566000
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4566000
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13441000
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 13441000
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13441000
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 13441000
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.071899
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.071899
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.cpu.icache.tags.replacements 70
|
||||
system.cpu.icache.tags.tagsinuse 96.586088
|
||||
system.cpu.icache.tags.total_refs 4779
|
||||
system.cpu.icache.tags.sampled_refs 249
|
||||
system.cpu.icache.tags.avg_refs 19.192771
|
||||
system.cpu.icache.tags.warmup_cycle 0
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 96.586088
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.377289
|
||||
system.cpu.icache.tags.occ_percent::total 0.377289
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 179
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 48
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 131
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.699219
|
||||
system.cpu.icache.tags.tag_accesses 10305
|
||||
system.cpu.icache.tags.data_accesses 10305
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4779
|
||||
system.cpu.icache.ReadReq_hits::total 4779
|
||||
system.cpu.icache.demand_hits::cpu.inst 4779
|
||||
system.cpu.icache.demand_hits::total 4779
|
||||
system.cpu.icache.overall_hits::cpu.inst 4779
|
||||
system.cpu.icache.overall_hits::total 4779
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 249
|
||||
system.cpu.icache.ReadReq_misses::total 249
|
||||
system.cpu.icache.demand_misses::cpu.inst 249
|
||||
system.cpu.icache.demand_misses::total 249
|
||||
system.cpu.icache.overall_misses::cpu.inst 249
|
||||
system.cpu.icache.overall_misses::total 249
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25472000
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25472000
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25472000
|
||||
system.cpu.icache.demand_miss_latency::total 25472000
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25472000
|
||||
system.cpu.icache.overall_miss_latency::total 25472000
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5028
|
||||
system.cpu.icache.ReadReq_accesses::total 5028
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5028
|
||||
system.cpu.icache.demand_accesses::total 5028
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5028
|
||||
system.cpu.icache.overall_accesses::total 5028
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.049523
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.049523
|
||||
system.cpu.icache.demand_miss_rate::total 0.049523
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.049523
|
||||
system.cpu.icache.overall_miss_rate::total 0.049523
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755
|
||||
system.cpu.icache.demand_avg_miss_latency::total 102297.188755
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755
|
||||
system.cpu.icache.overall_avg_miss_latency::total 102297.188755
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.icache.blocked_cycles::no_targets 0
|
||||
system.cpu.icache.blocked::no_mshrs 0
|
||||
system.cpu.icache.blocked::no_targets 0
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 249
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 249
|
||||
system.cpu.icache.demand_mshr_misses::total 249
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 249
|
||||
system.cpu.icache.overall_mshr_misses::total 249
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24974000
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 24974000
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24974000
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 24974000
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24974000
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 24974000
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.049523
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.049523
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755
|
||||
system.l2bus.snoop_filter.tot_requests 461
|
||||
system.l2bus.snoop_filter.hit_single_requests 94
|
||||
system.l2bus.snoop_filter.hit_multi_requests 10
|
||||
system.l2bus.snoop_filter.tot_snoops 0
|
||||
system.l2bus.snoop_filter.hit_single_snoops 0
|
||||
system.l2bus.snoop_filter.hit_multi_snoops 0
|
||||
system.l2bus.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.l2bus.trans_dist::ReadResp 348
|
||||
system.l2bus.trans_dist::CleanEvict 70
|
||||
system.l2bus.trans_dist::ReadExReq 43
|
||||
system.l2bus.trans_dist::ReadExResp 43
|
||||
system.l2bus.trans_dist::ReadSharedReq 348
|
||||
system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568
|
||||
system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284
|
||||
system.l2bus.pkt_count::total 852
|
||||
system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088
|
||||
system.l2bus.pkt_size::total 25024
|
||||
system.l2bus.snoops 0
|
||||
system.l2bus.snoopTraffic 0
|
||||
system.l2bus.snoop_fanout::samples 391
|
||||
system.l2bus.snoop_fanout::mean 0.086957
|
||||
system.l2bus.snoop_fanout::stdev 0.282132
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.l2bus.snoop_fanout::0 357 91.30% 91.30%
|
||||
system.l2bus.snoop_fanout::1 34 8.70% 100.00%
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00%
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.l2bus.snoop_fanout::min_value 0
|
||||
system.l2bus.snoop_fanout::max_value 1
|
||||
system.l2bus.snoop_fanout::total 391
|
||||
system.l2bus.reqLayer0.occupancy 461000
|
||||
system.l2bus.reqLayer0.utilization 0.9
|
||||
system.l2bus.respLayer0.occupancy 747000
|
||||
system.l2bus.respLayer0.utilization 1.4
|
||||
system.l2bus.respLayer1.occupancy 426000
|
||||
system.l2bus.respLayer1.utilization 0.8
|
||||
system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.l2cache.tags.replacements 0
|
||||
system.l2cache.tags.tagsinuse 184.362995
|
||||
system.l2cache.tags.total_refs 100
|
||||
system.l2cache.tags.sampled_refs 351
|
||||
system.l2cache.tags.avg_refs 0.284900
|
||||
system.l2cache.tags.warmup_cycle 0
|
||||
system.l2cache.tags.occ_blocks::cpu.inst 107.367017
|
||||
system.l2cache.tags.occ_blocks::cpu.data 76.995978
|
||||
system.l2cache.tags.occ_percent::cpu.inst 0.026213
|
||||
system.l2cache.tags.occ_percent::cpu.data 0.018798
|
||||
system.l2cache.tags.occ_percent::total 0.045010
|
||||
system.l2cache.tags.occ_task_id_blocks::1024 351
|
||||
system.l2cache.tags.age_task_id_blocks_1024::0 59
|
||||
system.l2cache.tags.age_task_id_blocks_1024::1 292
|
||||
system.l2cache.tags.occ_task_id_percent::1024 0.085693
|
||||
system.l2cache.tags.tag_accesses 3959
|
||||
system.l2cache.tags.data_accesses 3959
|
||||
system.l2cache.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.l2cache.ReadSharedReq_hits::cpu.inst 24
|
||||
system.l2cache.ReadSharedReq_hits::cpu.data 16
|
||||
system.l2cache.ReadSharedReq_hits::total 40
|
||||
system.l2cache.demand_hits::cpu.inst 24
|
||||
system.l2cache.demand_hits::cpu.data 16
|
||||
system.l2cache.demand_hits::total 40
|
||||
system.l2cache.overall_hits::cpu.inst 24
|
||||
system.l2cache.overall_hits::cpu.data 16
|
||||
system.l2cache.overall_hits::total 40
|
||||
system.l2cache.ReadExReq_misses::cpu.data 43
|
||||
system.l2cache.ReadExReq_misses::total 43
|
||||
system.l2cache.ReadSharedReq_misses::cpu.inst 225
|
||||
system.l2cache.ReadSharedReq_misses::cpu.data 83
|
||||
system.l2cache.ReadSharedReq_misses::total 308
|
||||
system.l2cache.demand_misses::cpu.inst 225
|
||||
system.l2cache.demand_misses::cpu.data 126
|
||||
system.l2cache.demand_misses::total 351
|
||||
system.l2cache.overall_misses::cpu.inst 225
|
||||
system.l2cache.overall_misses::cpu.data 126
|
||||
system.l2cache.overall_misses::total 351
|
||||
system.l2cache.ReadExReq_miss_latency::cpu.data 4437000
|
||||
system.l2cache.ReadExReq_miss_latency::total 4437000
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.inst 23683000
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.data 8214000
|
||||
system.l2cache.ReadSharedReq_miss_latency::total 31897000
|
||||
system.l2cache.demand_miss_latency::cpu.inst 23683000
|
||||
system.l2cache.demand_miss_latency::cpu.data 12651000
|
||||
system.l2cache.demand_miss_latency::total 36334000
|
||||
system.l2cache.overall_miss_latency::cpu.inst 23683000
|
||||
system.l2cache.overall_miss_latency::cpu.data 12651000
|
||||
system.l2cache.overall_miss_latency::total 36334000
|
||||
system.l2cache.ReadExReq_accesses::cpu.data 43
|
||||
system.l2cache.ReadExReq_accesses::total 43
|
||||
system.l2cache.ReadSharedReq_accesses::cpu.inst 249
|
||||
system.l2cache.ReadSharedReq_accesses::cpu.data 99
|
||||
system.l2cache.ReadSharedReq_accesses::total 348
|
||||
system.l2cache.demand_accesses::cpu.inst 249
|
||||
system.l2cache.demand_accesses::cpu.data 142
|
||||
system.l2cache.demand_accesses::total 391
|
||||
system.l2cache.overall_accesses::cpu.inst 249
|
||||
system.l2cache.overall_accesses::cpu.data 142
|
||||
system.l2cache.overall_accesses::total 391
|
||||
system.l2cache.ReadExReq_miss_rate::cpu.data 1
|
||||
system.l2cache.ReadExReq_miss_rate::total 1
|
||||
system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.903614
|
||||
system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384
|
||||
system.l2cache.ReadSharedReq_miss_rate::total 0.885057
|
||||
system.l2cache.demand_miss_rate::cpu.inst 0.903614
|
||||
system.l2cache.demand_miss_rate::cpu.data 0.887324
|
||||
system.l2cache.demand_miss_rate::total 0.897698
|
||||
system.l2cache.overall_miss_rate::cpu.inst 0.903614
|
||||
system.l2cache.overall_miss_rate::cpu.data 0.887324
|
||||
system.l2cache.overall_miss_rate::total 0.897698
|
||||
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103186.046512
|
||||
system.l2cache.ReadExReq_avg_miss_latency::total 103186.046512
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312
|
||||
system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778
|
||||
system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905
|
||||
system.l2cache.demand_avg_miss_latency::total 103515.669516
|
||||
system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778
|
||||
system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905
|
||||
system.l2cache.overall_avg_miss_latency::total 103515.669516
|
||||
system.l2cache.blocked_cycles::no_mshrs 0
|
||||
system.l2cache.blocked_cycles::no_targets 0
|
||||
system.l2cache.blocked::no_mshrs 0
|
||||
system.l2cache.blocked::no_targets 0
|
||||
system.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.l2cache.avg_blocked_cycles::no_targets nan
|
||||
system.l2cache.ReadExReq_mshr_misses::cpu.data 43
|
||||
system.l2cache.ReadExReq_mshr_misses::total 43
|
||||
system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225
|
||||
system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83
|
||||
system.l2cache.ReadSharedReq_mshr_misses::total 308
|
||||
system.l2cache.demand_mshr_misses::cpu.inst 225
|
||||
system.l2cache.demand_mshr_misses::cpu.data 126
|
||||
system.l2cache.demand_mshr_misses::total 351
|
||||
system.l2cache.overall_mshr_misses::cpu.inst 225
|
||||
system.l2cache.overall_mshr_misses::cpu.data 126
|
||||
system.l2cache.overall_mshr_misses::total 351
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577000
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::total 3577000
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19183000
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6554000
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::total 25737000
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.inst 19183000
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.data 10131000
|
||||
system.l2cache.demand_mshr_miss_latency::total 29314000
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.inst 19183000
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.data 10131000
|
||||
system.l2cache.overall_mshr_miss_latency::total 29314000
|
||||
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
|
||||
system.l2cache.ReadExReq_mshr_miss_rate::total 1
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057
|
||||
system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614
|
||||
system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324
|
||||
system.l2cache.demand_mshr_miss_rate::total 0.897698
|
||||
system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614
|
||||
system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324
|
||||
system.l2cache.overall_mshr_miss_rate::total 0.897698
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905
|
||||
system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905
|
||||
system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516
|
||||
system.membus.snoop_filter.tot_requests 351
|
||||
system.membus.snoop_filter.hit_single_requests 0
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 52453000
|
||||
system.membus.trans_dist::ReadResp 308
|
||||
system.membus.trans_dist::ReadExReq 43
|
||||
system.membus.trans_dist::ReadExResp 43
|
||||
system.membus.trans_dist::ReadSharedReq 308
|
||||
system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702
|
||||
system.membus.pkt_count::total 702
|
||||
system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464
|
||||
system.membus.pkt_size::total 22464
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 351
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 351 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 351
|
||||
system.membus.reqLayer0.occupancy 351000
|
||||
system.membus.reqLayer0.utilization 0.7
|
||||
system.membus.respLayer0.occupancy 1866250
|
||||
system.membus.respLayer0.utilization 3.6
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,267 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler mem_ctrl membus
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.mem_ctrl
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[2]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
children=voltage_domain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.clk_domain.voltage_domain
|
||||
|
||||
[system.clk_domain.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=-1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[1]
|
||||
icache_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=MipsTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=MipsInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=MipsISA
|
||||
eventq_index=0
|
||||
num_threads=1
|
||||
num_vpes=1
|
||||
system=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=MipsTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=tests/test-progs/hello/bin/mips/linux/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.mem_ctrl]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:536870911:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.mem_ctrl.port
|
||||
slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
@@ -1,16 +0,0 @@
|
||||
Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simout
|
||||
Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 13 2016 20:36:34
|
||||
gem5 started Oct 13 2016 20:36:59
|
||||
gem5 executing on e108600-lin, pid 36838
|
||||
command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Beginning simulation!
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello World!
|
||||
Exiting @ tick 423127000 because target called exit()
|
||||
@@ -1,403 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000423 # Number of seconds simulated
|
||||
sim_ticks 423127000 # Number of ticks simulated
|
||||
final_tick 423127000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 225323 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 225118 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 16871799532 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 632064 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 5641 # Number of instructions simulated
|
||||
sim_ops 5641 # Number of ops (including micro ops) simulated
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states
|
||||
system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory
|
||||
system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory
|
||||
system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory
|
||||
system.mem_ctrl.bytes_inst_read::cpu.inst 22568 # Number of instructions bytes read from this memory
|
||||
system.mem_ctrl.bytes_inst_read::total 22568 # Number of instructions bytes read from this memory
|
||||
system.mem_ctrl.bytes_written::cpu.data 3601 # Number of bytes written to this memory
|
||||
system.mem_ctrl.bytes_written::total 3601 # Number of bytes written to this memory
|
||||
system.mem_ctrl.num_reads::cpu.inst 5642 # Number of read requests responded to by this memory
|
||||
system.mem_ctrl.num_reads::cpu.data 1135 # Number of read requests responded to by this memory
|
||||
system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory
|
||||
system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory
|
||||
system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory
|
||||
system.mem_ctrl.bw_read::cpu.inst 53336232 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_read::cpu.data 10164797 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_read::total 63501029 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_inst_read::cpu.inst 53336232 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_inst_read::total 53336232 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_write::cpu.data 8510447 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_write::total 8510447 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::cpu.inst 53336232 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::cpu.data 18675244 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::total 72011476 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.readReqs 6778 # Number of read requests accepted
|
||||
system.mem_ctrl.writeReqs 901 # Number of write requests accepted
|
||||
system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrl.bytesReadDRAM 427712 # Total number of bytes read from DRAM
|
||||
system.mem_ctrl.bytesReadWrQ 6080 # Total number of bytes read from write queue
|
||||
system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM
|
||||
system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side
|
||||
system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side
|
||||
system.mem_ctrl.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrl.mergedWrBursts 808 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrl.perBankRdBursts::0 275 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::4 215 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::5 18 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::7 516 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::11 350 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::15 49 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::7 5 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::9 7 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::11 2 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::12 30 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::14 19 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrl.totGap 423050000 # Total gap between requests
|
||||
system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::0 1 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::2 900 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.rdQLenPdf::0 6683 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::17 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::18 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::19 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::20 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::21 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::22 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::23 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::24 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::25 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::26 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::27 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::28 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.bytesPerActivate::samples 846 # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::mean 508.141844 # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::gmean 296.960814 # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::stdev 409.521445 # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::0-127 262 30.97% 30.97% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::128-255 81 9.57% 40.54% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::256-383 50 5.91% 46.45% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::384-511 56 6.62% 53.07% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::512-639 41 4.85% 57.92% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::640-767 45 5.32% 63.24% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::768-895 28 3.31% 66.55% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::896-1023 22 2.60% 69.15% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::1024-1151 261 30.85% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::total 846 # Bytes accessed per row activation
|
||||
system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes
|
||||
system.mem_ctrl.rdPerTurnAround::mean 1385.500000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrl.rdPerTurnAround::gmean 1320.719140 # Reads before turning the bus around for writes
|
||||
system.mem_ctrl.rdPerTurnAround::stdev 457.578044 # Reads before turning the bus around for writes
|
||||
system.mem_ctrl.rdPerTurnAround::768-831 1 25.00% 25.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes
|
||||
system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads
|
||||
system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
|
||||
system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
|
||||
system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads
|
||||
system.mem_ctrl.totQLat 74613750 # Total ticks spent queuing
|
||||
system.mem_ctrl.totMemAccLat 199920000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrl.totBusLat 33415000 # Total ticks spent in databus transfers
|
||||
system.mem_ctrl.avgQLat 11164.71 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrl.avgMemAccLat 29914.71 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrl.avgRdBW 1010.84 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgWrBW 9.68 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgRdBWSys 63.51 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgWrBWSys 8.51 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrl.busUtil 7.97 # Data bus utilization in percentage
|
||||
system.mem_ctrl.busUtilRead 7.90 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrl.busUtilWrite 0.08 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrl.avgWrQLen 22.62 # Average write queue length when enqueuing
|
||||
system.mem_ctrl.readRowHits 5839 # Number of row buffer hits during reads
|
||||
system.mem_ctrl.writeRowHits 57 # Number of row buffer hits during writes
|
||||
system.mem_ctrl.readRowHitRate 87.37 # Row buffer hit rate for reads
|
||||
system.mem_ctrl.writeRowHitRate 61.29 # Row buffer hit rate for writes
|
||||
system.mem_ctrl.avgGap 55091.81 # Average gap between requests
|
||||
system.mem_ctrl.pageHitRate 87.01 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrl_0.actEnergy 985320 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrl_0.preEnergy 519915 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrl_0.readEnergy 8061060 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrl_0.writeEnergy 26100 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrl_0.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrl_0.actBackEnergy 21232500 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrl_0.preBackEnergy 1932000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrl_0.actPowerDownEnergy 84890100 # Energy for active power-down per rank (pJ)
|
||||
system.mem_ctrl_0.prePowerDownEnergy 43723680 # Energy for precharge power-down per rank (pJ)
|
||||
system.mem_ctrl_0.selfRefreshEnergy 22684200 # Energy for self refresh per rank (pJ)
|
||||
system.mem_ctrl_0.totalEnergy 217245435 # Total energy per rank (pJ)
|
||||
system.mem_ctrl_0.averagePower 513.427832 # Core power per rank (mW)
|
||||
system.mem_ctrl_0.totalIdleTime 369366500 # Total Idle time Per DRAM Rank
|
||||
system.mem_ctrl_0.memoryStateTime::IDLE 2976000 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::REF 14106000 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::SREF 71507250 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::PRE_PDN 113857500 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::ACT 34569250 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::ACT_PDN 186111000 # Time in different power states
|
||||
system.mem_ctrl_1.actEnergy 5090820 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrl_1.preEnergy 2690655 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrl_1.readEnergy 39648420 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrl_1.writeEnergy 307980 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrl_1.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrl_1.actBackEnergy 77391750 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrl_1.preBackEnergy 1169760 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrl_1.actPowerDownEnergy 113578770 # Energy for active power-down per rank (pJ)
|
||||
system.mem_ctrl_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ)
|
||||
system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
||||
system.mem_ctrl_1.totalEnergy 273562635 # Total energy per rank (pJ)
|
||||
system.mem_ctrl_1.averagePower 646.525303 # Core power per rank (mW)
|
||||
system.mem_ctrl_1.totalIdleTime 250424500 # Total Idle time Per DRAM Rank
|
||||
system.mem_ctrl_1.memoryStateTime::IDLE 900000 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::REF 14040000 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::PRE_PDN 1291250 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::ACT 157762500 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::ACT_PDN 249133250 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.numSyscalls 7 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 423127000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 423127 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5641 # Number of instructions committed
|
||||
system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 191 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4957 # number of integer instructions
|
||||
system.cpu.num_fp_insts 2 # number of float instructions
|
||||
system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2037 # number of memory refs
|
||||
system.cpu.num_load_insts 1135 # Number of load instructions
|
||||
system.cpu.num_store_insts 902 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 423127 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 886 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5642 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 6778 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 6777 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 901 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 901 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11285 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 15357 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7902 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 30470 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 7679 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7679 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7679 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.0 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 12855500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 3.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3550250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,434 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.mem_ctrl
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[1]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
children=voltage_domain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.clk_domain.voltage_domain
|
||||
|
||||
[system.clk_domain.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=-1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=65536
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.l2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=65536
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=MipsTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=16384
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.l2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=16384
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=MipsInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=MipsISA
|
||||
eventq_index=0
|
||||
num_threads=1
|
||||
num_vpes=1
|
||||
system=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=MipsTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=tests/test-progs/hello/bin/mips/linux/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.l2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.l2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.l2bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=262144
|
||||
|
||||
[system.mem_ctrl]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:536870911:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.mem_ctrl.port
|
||||
slave=system.l2cache.mem_side system.system_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
@@ -1,16 +0,0 @@
|
||||
Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simout
|
||||
Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 13 2016 20:36:34
|
||||
gem5 started Oct 13 2016 20:36:59
|
||||
gem5 executing on e108600-lin, pid 36839
|
||||
command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Beginning simulation!
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello World!
|
||||
Exiting @ tick 62333000 because target called exit()
|
||||
@@ -1,732 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000062 # Number of seconds simulated
|
||||
sim_ticks 62333000 # Number of ticks simulated
|
||||
final_tick 62333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 472885 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 471880 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5205204018 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 636424 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5641 # Number of instructions simulated
|
||||
sim_ops 5641 # Number of ops (including micro ops) simulated
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
|
||||
system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory
|
||||
system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory
|
||||
system.mem_ctrl.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory
|
||||
system.mem_ctrl.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory
|
||||
system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory
|
||||
system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory
|
||||
system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory
|
||||
system.mem_ctrl.bw_read::cpu.inst 300835833 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_read::cpu.data 140663854 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_read::total 441499687 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_inst_read::cpu.inst 300835833 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_inst_read::total 300835833 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::cpu.inst 300835833 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::cpu.data 140663854 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::total 441499687 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.readReqs 430 # Number of read requests accepted
|
||||
system.mem_ctrl.writeReqs 0 # Number of write requests accepted
|
||||
system.mem_ctrl.readBursts 430 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrl.bytesReadDRAM 27520 # Total number of bytes read from DRAM
|
||||
system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.mem_ctrl.bytesReadSys 27520 # Total read bytes from the system interface side
|
||||
system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrl.perBankRdBursts::0 25 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::4 6 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::5 3 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::6 11 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::7 49 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::8 53 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::9 74 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::10 34 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::11 19 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::12 50 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::13 27 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::14 72 # Per bank write bursts
|
||||
system.mem_ctrl.perBankRdBursts::15 7 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrl.totGap 62196000 # Total gap between requests
|
||||
system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::6 430 # Read request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.mem_ctrl.rdQLenPdf::0 430 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::mean 241.840708 # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::gmean 173.064480 # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::stdev 223.138673 # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::128-255 41 36.28% 62.83% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::256-383 20 17.70% 80.53% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::384-511 8 7.08% 87.61% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.04% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::640-767 2 1.77% 93.81% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::768-895 3 2.65% 96.46% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::896-1023 1 0.88% 97.35% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation
|
||||
system.mem_ctrl.totQLat 6850250 # Total ticks spent queuing
|
||||
system.mem_ctrl.totMemAccLat 14912750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers
|
||||
system.mem_ctrl.avgQLat 15930.81 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrl.avgMemAccLat 34680.81 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrl.avgRdBW 441.50 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgRdBWSys 441.50 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrl.busUtil 3.45 # Data bus utilization in percentage
|
||||
system.mem_ctrl.busUtilRead 3.45 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.mem_ctrl.readRowHits 316 # Number of row buffer hits during reads
|
||||
system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.mem_ctrl.readRowHitRate 73.49 # Row buffer hit rate for reads
|
||||
system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.mem_ctrl.avgGap 144641.86 # Average gap between requests
|
||||
system.mem_ctrl.pageHitRate 73.49 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrl_0.actEnergy 192780 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrl_0.preEnergy 98670 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrl_0.readEnergy 671160 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrl_0.actBackEnergy 2176830 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrl_0.preBackEnergy 210240 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrl_0.actPowerDownEnergy 19527630 # Energy for active power-down per rank (pJ)
|
||||
system.mem_ctrl_0.prePowerDownEnergy 3815040 # Energy for precharge power-down per rank (pJ)
|
||||
system.mem_ctrl_0.selfRefreshEnergy 1573140 # Energy for self refresh per rank (pJ)
|
||||
system.mem_ctrl_0.totalEnergy 33182610 # Total energy per rank (pJ)
|
||||
system.mem_ctrl_0.averagePower 532.337778 # Core power per rank (mW)
|
||||
system.mem_ctrl_0.totalIdleTime 56494000 # Total Idle time Per DRAM Rank
|
||||
system.mem_ctrl_0.memoryStateTime::IDLE 323000 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::REF 2086000 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::SREF 4253250 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::PRE_PDN 9935000 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::ACT 2911750 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::ACT_PDN 42824000 # Time in different power states
|
||||
system.mem_ctrl_1.actEnergy 621180 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrl_1.preEnergy 330165 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrl_1.readEnergy 2399040 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrl_1.actBackEnergy 5632170 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrl_1.preBackEnergy 168480 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrl_1.actPowerDownEnergy 22617030 # Energy for active power-down per rank (pJ)
|
||||
system.mem_ctrl_1.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ)
|
||||
system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
||||
system.mem_ctrl_1.totalEnergy 36749505 # Total energy per rank (pJ)
|
||||
system.mem_ctrl_1.averagePower 587.463363 # Core power per rank (mW)
|
||||
system.mem_ctrl_1.totalIdleTime 49768000 # Total Idle time Per DRAM Rank
|
||||
system.mem_ctrl_1.memoryStateTime::IDLE 176000 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::REF 1843250 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::PRE_PDN 167500 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::ACT 10545750 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::ACT_PDN 49600500 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.numSyscalls 7 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 62333 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5641 # Number of instructions committed
|
||||
system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 191 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4957 # number of integer instructions
|
||||
system.cpu.num_fp_insts 2 # number of float instructions
|
||||
system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2037 # number of memory refs
|
||||
system.cpu.num_load_insts 1135 # Number of load instructions
|
||||
system.cpu.num_store_insts 902 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 62333 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 886 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5642 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 86.045434 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.045434 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.084029 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.084029 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1899 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 137 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10089000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10089000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5605000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5605000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 15694000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 15694000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 15694000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 15694000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115965.517241 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 115965.517241 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 112100 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 112100 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 114554.744526 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 114554.744526 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9915000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9915000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5505000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5505000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15420000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 15420000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15420000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 15420000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 113965.517241 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 113965.517241 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 110100 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 110100 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 94 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 109.768952 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 109.768952 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.428785 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.428785 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 11583 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 5346 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 5346 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 5346 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 297 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 297 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32151000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32151000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32151000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32151000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32151000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32151000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052632 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.052632 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108252.525253 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 108252.525253 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 108252.525253 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 108252.525253 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31557000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 31557000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31557000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 31557000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31557000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 31557000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106252.525253 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106252.525253 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency
|
||||
system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter.
|
||||
system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.l2bus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.l2bus.trans_dist::ReadResp 384 # Transaction distribution
|
||||
system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadExResp 50 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadSharedReq 384 # Transaction distribution
|
||||
system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_count::total 962 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 19008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.l2bus.snoop_fanout::samples 434 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 434 100.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 434 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks)
|
||||
system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks)
|
||||
system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks)
|
||||
system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.l2cache.tags.replacements 0 # number of replacements
|
||||
system.l2cache.tags.tagsinuse 215.766788 # Cycle average of tags in use
|
||||
system.l2cache.tags.total_refs 98 # Total number of references to valid blocks.
|
||||
system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks.
|
||||
system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks.
|
||||
system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2cache.tags.occ_blocks::cpu.inst 129.675199 # Average occupied blocks per requestor
|
||||
system.l2cache.tags.occ_blocks::cpu.data 86.091590 # Average occupied blocks per requestor
|
||||
system.l2cache.tags.occ_percent::cpu.inst 0.031659 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_percent::cpu.data 0.021018 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_percent::total 0.052677 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
|
||||
system.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
|
||||
system.l2cache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
|
||||
system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id
|
||||
system.l2cache.tags.tag_accesses 4654 # Number of tag accesses
|
||||
system.l2cache.tags.data_accesses 4654 # Number of data accesses
|
||||
system.l2cache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits
|
||||
system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits
|
||||
system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits
|
||||
system.l2cache.demand_hits::total 4 # number of demand (read+write) hits
|
||||
system.l2cache.overall_hits::cpu.inst 4 # number of overall hits
|
||||
system.l2cache.overall_hits::total 4 # number of overall hits
|
||||
system.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
|
||||
system.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
|
||||
system.l2cache.ReadSharedReq_misses::cpu.inst 293 # number of ReadSharedReq misses
|
||||
system.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses
|
||||
system.l2cache.ReadSharedReq_misses::total 380 # number of ReadSharedReq misses
|
||||
system.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses
|
||||
system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses
|
||||
system.l2cache.demand_misses::total 430 # number of demand (read+write) misses
|
||||
system.l2cache.overall_misses::cpu.inst 293 # number of overall misses
|
||||
system.l2cache.overall_misses::cpu.data 137 # number of overall misses
|
||||
system.l2cache.overall_misses::total 430 # number of overall misses
|
||||
system.l2cache.ReadExReq_miss_latency::cpu.data 5355000 # number of ReadExReq miss cycles
|
||||
system.l2cache.ReadExReq_miss_latency::total 5355000 # number of ReadExReq miss cycles
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.inst 30582000 # number of ReadSharedReq miss cycles
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.data 9654000 # number of ReadSharedReq miss cycles
|
||||
system.l2cache.ReadSharedReq_miss_latency::total 40236000 # number of ReadSharedReq miss cycles
|
||||
system.l2cache.demand_miss_latency::cpu.inst 30582000 # number of demand (read+write) miss cycles
|
||||
system.l2cache.demand_miss_latency::cpu.data 15009000 # number of demand (read+write) miss cycles
|
||||
system.l2cache.demand_miss_latency::total 45591000 # number of demand (read+write) miss cycles
|
||||
system.l2cache.overall_miss_latency::cpu.inst 30582000 # number of overall miss cycles
|
||||
system.l2cache.overall_miss_latency::cpu.data 15009000 # number of overall miss cycles
|
||||
system.l2cache.overall_miss_latency::total 45591000 # number of overall miss cycles
|
||||
system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2cache.ReadSharedReq_accesses::total 384 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses
|
||||
system.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses
|
||||
system.l2cache.demand_accesses::total 434 # number of demand (read+write) accesses
|
||||
system.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses
|
||||
system.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses
|
||||
system.l2cache.overall_accesses::total 434 # number of overall (read+write) accesses
|
||||
system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.986532 # miss rate for ReadSharedReq accesses
|
||||
system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
|
||||
system.l2cache.ReadSharedReq_miss_rate::total 0.989583 # miss rate for ReadSharedReq accesses
|
||||
system.l2cache.demand_miss_rate::cpu.inst 0.986532 # miss rate for demand accesses
|
||||
system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.l2cache.demand_miss_rate::total 0.990783 # miss rate for demand accesses
|
||||
system.l2cache.overall_miss_rate::cpu.inst 0.986532 # miss rate for overall accesses
|
||||
system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses
|
||||
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 107100 # average ReadExReq miss latency
|
||||
system.l2cache.ReadExReq_avg_miss_latency::total 107100 # average ReadExReq miss latency
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104375.426621 # average ReadSharedReq miss latency
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110965.517241 # average ReadSharedReq miss latency
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::total 105884.210526 # average ReadSharedReq miss latency
|
||||
system.l2cache.demand_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency
|
||||
system.l2cache.demand_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency
|
||||
system.l2cache.demand_avg_miss_latency::total 106025.581395 # average overall miss latency
|
||||
system.l2cache.overall_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency
|
||||
system.l2cache.overall_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency
|
||||
system.l2cache.overall_avg_miss_latency::total 106025.581395 # average overall miss latency
|
||||
system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
|
||||
system.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
|
||||
system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 293 # number of ReadSharedReq MSHR misses
|
||||
system.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses
|
||||
system.l2cache.ReadSharedReq_mshr_misses::total 380 # number of ReadSharedReq MSHR misses
|
||||
system.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
|
||||
system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
|
||||
system.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
|
||||
system.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
|
||||
system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
|
||||
system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4355000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::total 4355000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 24722000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7914000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::total 32636000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.inst 24722000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.data 12269000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2cache.demand_mshr_miss_latency::total 36991000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.inst 24722000 # number of overall MSHR miss cycles
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.data 12269000 # number of overall MSHR miss cycles
|
||||
system.l2cache.overall_mshr_miss_latency::total 36991000 # number of overall MSHR miss cycles
|
||||
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989583 # mshr miss rate for ReadSharedReq accesses
|
||||
system.l2cache.demand_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for demand accesses
|
||||
system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.l2cache.demand_mshr_miss_rate::total 0.990783 # mshr miss rate for demand accesses
|
||||
system.l2cache.overall_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for overall accesses
|
||||
system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87100 # average ReadExReq mshr miss latency
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 87100 # average ReadExReq mshr miss latency
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84375.426621 # average ReadSharedReq mshr miss latency
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90965.517241 # average ReadSharedReq mshr miss latency
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85884.210526 # average ReadSharedReq mshr miss latency
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency
|
||||
system.l2cache.demand_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency
|
||||
system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 380 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 860 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 27520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 430 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 430 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 2298250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 3.7 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,266 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler mem_ctrl membus
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.mem_ctrl
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[2]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
children=voltage_domain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.clk_domain.voltage_domain
|
||||
|
||||
[system.clk_domain.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=-1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[1]
|
||||
icache_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=SparcISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=tests/test-progs/hello/bin/sparc/linux/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.mem_ctrl]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:536870911:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.mem_ctrl.port
|
||||
slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
@@ -1,13 +0,0 @@
|
||||
Redirecting stdout to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple/simout
|
||||
Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 18:41:19
|
||||
gem5 started Apr 3 2017 18:41:38
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64860
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Beginning simulation!
|
||||
Hello World!Exiting @ tick 380341000 because exiting with last active thread context
|
||||
@@ -1,386 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000380
|
||||
sim_ticks 380341000
|
||||
final_tick 380341000
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 164409
|
||||
host_op_rate 164322
|
||||
host_tick_rate 11259796640
|
||||
host_mem_usage 644796
|
||||
host_seconds 0.03
|
||||
sim_insts 5548
|
||||
sim_ops 5548
|
||||
system.clk_domain.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 380341000
|
||||
system.mem_ctrl.bytes_read::cpu.inst 22364
|
||||
system.mem_ctrl.bytes_read::cpu.data 4640
|
||||
system.mem_ctrl.bytes_read::total 27004
|
||||
system.mem_ctrl.bytes_inst_read::cpu.inst 22364
|
||||
system.mem_ctrl.bytes_inst_read::total 22364
|
||||
system.mem_ctrl.bytes_written::cpu.data 5065
|
||||
system.mem_ctrl.bytes_written::total 5065
|
||||
system.mem_ctrl.num_reads::cpu.inst 5591
|
||||
system.mem_ctrl.num_reads::cpu.data 718
|
||||
system.mem_ctrl.num_reads::total 6309
|
||||
system.mem_ctrl.num_writes::cpu.data 673
|
||||
system.mem_ctrl.num_writes::total 673
|
||||
system.mem_ctrl.bw_read::cpu.inst 58799866
|
||||
system.mem_ctrl.bw_read::cpu.data 12199579
|
||||
system.mem_ctrl.bw_read::total 70999445
|
||||
system.mem_ctrl.bw_inst_read::cpu.inst 58799866
|
||||
system.mem_ctrl.bw_inst_read::total 58799866
|
||||
system.mem_ctrl.bw_write::cpu.data 13316997
|
||||
system.mem_ctrl.bw_write::total 13316997
|
||||
system.mem_ctrl.bw_total::cpu.inst 58799866
|
||||
system.mem_ctrl.bw_total::cpu.data 25516576
|
||||
system.mem_ctrl.bw_total::total 84316442
|
||||
system.mem_ctrl.readReqs 6310
|
||||
system.mem_ctrl.writeReqs 673
|
||||
system.mem_ctrl.readBursts 6310
|
||||
system.mem_ctrl.writeBursts 673
|
||||
system.mem_ctrl.bytesReadDRAM 397760
|
||||
system.mem_ctrl.bytesReadWrQ 6080
|
||||
system.mem_ctrl.bytesWritten 6144
|
||||
system.mem_ctrl.bytesReadSys 27008
|
||||
system.mem_ctrl.bytesWrittenSys 5065
|
||||
system.mem_ctrl.servicedByWrQ 95
|
||||
system.mem_ctrl.mergedWrBursts 548
|
||||
system.mem_ctrl.neitherReadNorWriteReqs 0
|
||||
system.mem_ctrl.perBankRdBursts::0 220
|
||||
system.mem_ctrl.perBankRdBursts::1 84
|
||||
system.mem_ctrl.perBankRdBursts::2 2
|
||||
system.mem_ctrl.perBankRdBursts::3 199
|
||||
system.mem_ctrl.perBankRdBursts::4 0
|
||||
system.mem_ctrl.perBankRdBursts::5 1004
|
||||
system.mem_ctrl.perBankRdBursts::6 1555
|
||||
system.mem_ctrl.perBankRdBursts::7 875
|
||||
system.mem_ctrl.perBankRdBursts::8 710
|
||||
system.mem_ctrl.perBankRdBursts::9 348
|
||||
system.mem_ctrl.perBankRdBursts::10 99
|
||||
system.mem_ctrl.perBankRdBursts::11 623
|
||||
system.mem_ctrl.perBankRdBursts::12 56
|
||||
system.mem_ctrl.perBankRdBursts::13 162
|
||||
system.mem_ctrl.perBankRdBursts::14 200
|
||||
system.mem_ctrl.perBankRdBursts::15 78
|
||||
system.mem_ctrl.perBankWrBursts::0 0
|
||||
system.mem_ctrl.perBankWrBursts::1 0
|
||||
system.mem_ctrl.perBankWrBursts::2 0
|
||||
system.mem_ctrl.perBankWrBursts::3 0
|
||||
system.mem_ctrl.perBankWrBursts::4 0
|
||||
system.mem_ctrl.perBankWrBursts::5 16
|
||||
system.mem_ctrl.perBankWrBursts::6 42
|
||||
system.mem_ctrl.perBankWrBursts::7 19
|
||||
system.mem_ctrl.perBankWrBursts::8 0
|
||||
system.mem_ctrl.perBankWrBursts::9 5
|
||||
system.mem_ctrl.perBankWrBursts::10 0
|
||||
system.mem_ctrl.perBankWrBursts::11 0
|
||||
system.mem_ctrl.perBankWrBursts::12 4
|
||||
system.mem_ctrl.perBankWrBursts::13 10
|
||||
system.mem_ctrl.perBankWrBursts::14 0
|
||||
system.mem_ctrl.perBankWrBursts::15 0
|
||||
system.mem_ctrl.numRdRetry 0
|
||||
system.mem_ctrl.numWrRetry 0
|
||||
system.mem_ctrl.totGap 380264000
|
||||
system.mem_ctrl.readPktSize::0 88
|
||||
system.mem_ctrl.readPktSize::1 2
|
||||
system.mem_ctrl.readPktSize::2 5711
|
||||
system.mem_ctrl.readPktSize::3 509
|
||||
system.mem_ctrl.readPktSize::4 0
|
||||
system.mem_ctrl.readPktSize::5 0
|
||||
system.mem_ctrl.readPktSize::6 0
|
||||
system.mem_ctrl.writePktSize::0 13
|
||||
system.mem_ctrl.writePktSize::1 2
|
||||
system.mem_ctrl.writePktSize::2 54
|
||||
system.mem_ctrl.writePktSize::3 604
|
||||
system.mem_ctrl.writePktSize::4 0
|
||||
system.mem_ctrl.writePktSize::5 0
|
||||
system.mem_ctrl.writePktSize::6 0
|
||||
system.mem_ctrl.rdQLenPdf::0 6215
|
||||
system.mem_ctrl.rdQLenPdf::1 0
|
||||
system.mem_ctrl.rdQLenPdf::2 0
|
||||
system.mem_ctrl.rdQLenPdf::3 0
|
||||
system.mem_ctrl.rdQLenPdf::4 0
|
||||
system.mem_ctrl.rdQLenPdf::5 0
|
||||
system.mem_ctrl.rdQLenPdf::6 0
|
||||
system.mem_ctrl.rdQLenPdf::7 0
|
||||
system.mem_ctrl.rdQLenPdf::8 0
|
||||
system.mem_ctrl.rdQLenPdf::9 0
|
||||
system.mem_ctrl.rdQLenPdf::10 0
|
||||
system.mem_ctrl.rdQLenPdf::11 0
|
||||
system.mem_ctrl.rdQLenPdf::12 0
|
||||
system.mem_ctrl.rdQLenPdf::13 0
|
||||
system.mem_ctrl.rdQLenPdf::14 0
|
||||
system.mem_ctrl.rdQLenPdf::15 0
|
||||
system.mem_ctrl.rdQLenPdf::16 0
|
||||
system.mem_ctrl.rdQLenPdf::17 0
|
||||
system.mem_ctrl.rdQLenPdf::18 0
|
||||
system.mem_ctrl.rdQLenPdf::19 0
|
||||
system.mem_ctrl.rdQLenPdf::20 0
|
||||
system.mem_ctrl.rdQLenPdf::21 0
|
||||
system.mem_ctrl.rdQLenPdf::22 0
|
||||
system.mem_ctrl.rdQLenPdf::23 0
|
||||
system.mem_ctrl.rdQLenPdf::24 0
|
||||
system.mem_ctrl.rdQLenPdf::25 0
|
||||
system.mem_ctrl.rdQLenPdf::26 0
|
||||
system.mem_ctrl.rdQLenPdf::27 0
|
||||
system.mem_ctrl.rdQLenPdf::28 0
|
||||
system.mem_ctrl.rdQLenPdf::29 0
|
||||
system.mem_ctrl.rdQLenPdf::30 0
|
||||
system.mem_ctrl.rdQLenPdf::31 0
|
||||
system.mem_ctrl.wrQLenPdf::0 1
|
||||
system.mem_ctrl.wrQLenPdf::1 1
|
||||
system.mem_ctrl.wrQLenPdf::2 1
|
||||
system.mem_ctrl.wrQLenPdf::3 1
|
||||
system.mem_ctrl.wrQLenPdf::4 1
|
||||
system.mem_ctrl.wrQLenPdf::5 1
|
||||
system.mem_ctrl.wrQLenPdf::6 1
|
||||
system.mem_ctrl.wrQLenPdf::7 1
|
||||
system.mem_ctrl.wrQLenPdf::8 1
|
||||
system.mem_ctrl.wrQLenPdf::9 1
|
||||
system.mem_ctrl.wrQLenPdf::10 1
|
||||
system.mem_ctrl.wrQLenPdf::11 1
|
||||
system.mem_ctrl.wrQLenPdf::12 1
|
||||
system.mem_ctrl.wrQLenPdf::13 1
|
||||
system.mem_ctrl.wrQLenPdf::14 1
|
||||
system.mem_ctrl.wrQLenPdf::15 1
|
||||
system.mem_ctrl.wrQLenPdf::16 1
|
||||
system.mem_ctrl.wrQLenPdf::17 7
|
||||
system.mem_ctrl.wrQLenPdf::18 7
|
||||
system.mem_ctrl.wrQLenPdf::19 7
|
||||
system.mem_ctrl.wrQLenPdf::20 7
|
||||
system.mem_ctrl.wrQLenPdf::21 7
|
||||
system.mem_ctrl.wrQLenPdf::22 7
|
||||
system.mem_ctrl.wrQLenPdf::23 7
|
||||
system.mem_ctrl.wrQLenPdf::24 7
|
||||
system.mem_ctrl.wrQLenPdf::25 7
|
||||
system.mem_ctrl.wrQLenPdf::26 7
|
||||
system.mem_ctrl.wrQLenPdf::27 7
|
||||
system.mem_ctrl.wrQLenPdf::28 7
|
||||
system.mem_ctrl.wrQLenPdf::29 6
|
||||
system.mem_ctrl.wrQLenPdf::30 6
|
||||
system.mem_ctrl.wrQLenPdf::31 6
|
||||
system.mem_ctrl.wrQLenPdf::32 6
|
||||
system.mem_ctrl.wrQLenPdf::33 0
|
||||
system.mem_ctrl.wrQLenPdf::34 0
|
||||
system.mem_ctrl.wrQLenPdf::35 0
|
||||
system.mem_ctrl.wrQLenPdf::36 0
|
||||
system.mem_ctrl.wrQLenPdf::37 0
|
||||
system.mem_ctrl.wrQLenPdf::38 0
|
||||
system.mem_ctrl.wrQLenPdf::39 0
|
||||
system.mem_ctrl.wrQLenPdf::40 0
|
||||
system.mem_ctrl.wrQLenPdf::41 0
|
||||
system.mem_ctrl.wrQLenPdf::42 0
|
||||
system.mem_ctrl.wrQLenPdf::43 0
|
||||
system.mem_ctrl.wrQLenPdf::44 0
|
||||
system.mem_ctrl.wrQLenPdf::45 0
|
||||
system.mem_ctrl.wrQLenPdf::46 0
|
||||
system.mem_ctrl.wrQLenPdf::47 0
|
||||
system.mem_ctrl.wrQLenPdf::48 0
|
||||
system.mem_ctrl.wrQLenPdf::49 0
|
||||
system.mem_ctrl.wrQLenPdf::50 0
|
||||
system.mem_ctrl.wrQLenPdf::51 0
|
||||
system.mem_ctrl.wrQLenPdf::52 0
|
||||
system.mem_ctrl.wrQLenPdf::53 0
|
||||
system.mem_ctrl.wrQLenPdf::54 0
|
||||
system.mem_ctrl.wrQLenPdf::55 0
|
||||
system.mem_ctrl.wrQLenPdf::56 0
|
||||
system.mem_ctrl.wrQLenPdf::57 0
|
||||
system.mem_ctrl.wrQLenPdf::58 0
|
||||
system.mem_ctrl.wrQLenPdf::59 0
|
||||
system.mem_ctrl.wrQLenPdf::60 0
|
||||
system.mem_ctrl.wrQLenPdf::61 0
|
||||
system.mem_ctrl.wrQLenPdf::62 0
|
||||
system.mem_ctrl.wrQLenPdf::63 0
|
||||
system.mem_ctrl.bytesPerActivate::samples 575
|
||||
system.mem_ctrl.bytesPerActivate::mean 700.438261
|
||||
system.mem_ctrl.bytesPerActivate::gmean 528.229400
|
||||
system.mem_ctrl.bytesPerActivate::stdev 375.888489
|
||||
system.mem_ctrl.bytesPerActivate::0-127 45 7.83% 7.83%
|
||||
system.mem_ctrl.bytesPerActivate::128-255 73 12.70% 20.52%
|
||||
system.mem_ctrl.bytesPerActivate::256-383 37 6.43% 26.96%
|
||||
system.mem_ctrl.bytesPerActivate::384-511 35 6.09% 33.04%
|
||||
system.mem_ctrl.bytesPerActivate::512-639 26 4.52% 37.57%
|
||||
system.mem_ctrl.bytesPerActivate::640-767 27 4.70% 42.26%
|
||||
system.mem_ctrl.bytesPerActivate::768-895 26 4.52% 46.78%
|
||||
system.mem_ctrl.bytesPerActivate::896-1023 27 4.70% 51.48%
|
||||
system.mem_ctrl.bytesPerActivate::1024-1151 279 48.52% 100.00%
|
||||
system.mem_ctrl.bytesPerActivate::total 575
|
||||
system.mem_ctrl.rdPerTurnAround::samples 6
|
||||
system.mem_ctrl.rdPerTurnAround::mean 772.166667
|
||||
system.mem_ctrl.rdPerTurnAround::gmean 643.154197
|
||||
system.mem_ctrl.rdPerTurnAround::stdev 524.176084
|
||||
system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33%
|
||||
system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00%
|
||||
system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67%
|
||||
system.mem_ctrl.rdPerTurnAround::896-959 1 16.67% 83.33%
|
||||
system.mem_ctrl.rdPerTurnAround::1664-1727 1 16.67% 100.00%
|
||||
system.mem_ctrl.rdPerTurnAround::total 6
|
||||
system.mem_ctrl.wrPerTurnAround::samples 6
|
||||
system.mem_ctrl.wrPerTurnAround::mean 16
|
||||
system.mem_ctrl.wrPerTurnAround::gmean 16.000000
|
||||
system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00%
|
||||
system.mem_ctrl.wrPerTurnAround::total 6
|
||||
system.mem_ctrl.totQLat 59680000
|
||||
system.mem_ctrl.totMemAccLat 176211250
|
||||
system.mem_ctrl.totBusLat 31075000
|
||||
system.mem_ctrl.avgQLat 9602.57
|
||||
system.mem_ctrl.avgBusLat 5000.00
|
||||
system.mem_ctrl.avgMemAccLat 28352.57
|
||||
system.mem_ctrl.avgRdBW 1045.80
|
||||
system.mem_ctrl.avgWrBW 16.15
|
||||
system.mem_ctrl.avgRdBWSys 71.01
|
||||
system.mem_ctrl.avgWrBWSys 13.32
|
||||
system.mem_ctrl.peakBW 12800.00
|
||||
system.mem_ctrl.busUtil 8.30
|
||||
system.mem_ctrl.busUtilRead 8.17
|
||||
system.mem_ctrl.busUtilWrite 0.13
|
||||
system.mem_ctrl.avgRdQLen 1.00
|
||||
system.mem_ctrl.avgWrQLen 23.12
|
||||
system.mem_ctrl.readRowHits 5650
|
||||
system.mem_ctrl.writeRowHits 83
|
||||
system.mem_ctrl.readRowHitRate 90.91
|
||||
system.mem_ctrl.writeRowHitRate 66.40
|
||||
system.mem_ctrl.avgGap 54455.68
|
||||
system.mem_ctrl.pageHitRate 90.43
|
||||
system.mem_ctrl_0.actEnergy 2598960
|
||||
system.mem_ctrl_0.preEnergy 1377585
|
||||
system.mem_ctrl_0.readEnergy 28124460
|
||||
system.mem_ctrl_0.writeEnergy 401940
|
||||
system.mem_ctrl_0.refreshEnergy 29502720.000000
|
||||
system.mem_ctrl_0.actBackEnergy 55884510
|
||||
system.mem_ctrl_0.preBackEnergy 903360
|
||||
system.mem_ctrl_0.actPowerDownEnergy 108619200
|
||||
system.mem_ctrl_0.prePowerDownEnergy 6618240
|
||||
system.mem_ctrl_0.selfRefreshEnergy 0
|
||||
system.mem_ctrl_0.totalEnergy 234030975
|
||||
system.mem_ctrl_0.averagePower 615.318415
|
||||
system.mem_ctrl_0.totalIdleTime 255286000
|
||||
system.mem_ctrl_0.memoryStateTime::IDLE 462000
|
||||
system.mem_ctrl_0.memoryStateTime::REF 12480000
|
||||
system.mem_ctrl_0.memoryStateTime::SREF 0
|
||||
system.mem_ctrl_0.memoryStateTime::PRE_PDN 17232500
|
||||
system.mem_ctrl_0.memoryStateTime::ACT 111848750
|
||||
system.mem_ctrl_0.memoryStateTime::ACT_PDN 238317750
|
||||
system.mem_ctrl_1.actEnergy 1527960
|
||||
system.mem_ctrl_1.preEnergy 804540
|
||||
system.mem_ctrl_1.readEnergy 16243500
|
||||
system.mem_ctrl_1.writeEnergy 99180
|
||||
system.mem_ctrl_1.refreshEnergy 28273440.000000
|
||||
system.mem_ctrl_1.actBackEnergy 35538930
|
||||
system.mem_ctrl_1.preBackEnergy 1997760
|
||||
system.mem_ctrl_1.actPowerDownEnergy 96272430
|
||||
system.mem_ctrl_1.prePowerDownEnergy 16892160
|
||||
system.mem_ctrl_1.selfRefreshEnergy 11758020
|
||||
system.mem_ctrl_1.totalEnergy 209407920
|
||||
system.mem_ctrl_1.averagePower 550.579039
|
||||
system.mem_ctrl_1.totalIdleTime 297220000
|
||||
system.mem_ctrl_1.memoryStateTime::IDLE 3473000
|
||||
system.mem_ctrl_1.memoryStateTime::REF 11978000
|
||||
system.mem_ctrl_1.memoryStateTime::SREF 42087750
|
||||
system.mem_ctrl_1.memoryStateTime::PRE_PDN 43986250
|
||||
system.mem_ctrl_1.memoryStateTime::ACT 67670000
|
||||
system.mem_ctrl_1.memoryStateTime::ACT_PDN 211146000
|
||||
system.pwrStateResidencyTicks::UNDEFINED 380341000
|
||||
system.cpu.workload.numSyscalls 11
|
||||
system.cpu.pwrStateResidencyTicks::ON 380341000
|
||||
system.cpu.numCycles 380341
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 5548
|
||||
system.cpu.committedOps 5548
|
||||
system.cpu.num_int_alu_accesses 4660
|
||||
system.cpu.num_fp_alu_accesses 0
|
||||
system.cpu.num_func_calls 146
|
||||
system.cpu.num_conditional_control_insts 835
|
||||
system.cpu.num_int_insts 4660
|
||||
system.cpu.num_fp_insts 0
|
||||
system.cpu.num_int_register_reads 10977
|
||||
system.cpu.num_int_register_writes 5062
|
||||
system.cpu.num_fp_register_reads 0
|
||||
system.cpu.num_fp_register_writes 0
|
||||
system.cpu.num_mem_refs 1404
|
||||
system.cpu.num_load_insts 726
|
||||
system.cpu.num_store_insts 678
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 380341
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 1187
|
||||
system.cpu.op_class::No_OpClass 173 3.09% 3.09%
|
||||
system.cpu.op_class::IntAlu 4014 71.79% 74.89%
|
||||
system.cpu.op_class::IntMult 0 0.00% 74.89%
|
||||
system.cpu.op_class::IntDiv 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89%
|
||||
system.cpu.op_class::MemRead 726 12.99% 87.87%
|
||||
system.cpu.op_class::MemWrite 678 12.13% 100.00%
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
|
||||
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 5591
|
||||
system.membus.snoop_filter.tot_requests 0
|
||||
system.membus.snoop_filter.hit_single_requests 0
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 380341000
|
||||
system.membus.trans_dist::ReadReq 6310
|
||||
system.membus.trans_dist::ReadResp 6309
|
||||
system.membus.trans_dist::WriteReq 673
|
||||
system.membus.trans_dist::WriteResp 673
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11183
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 2782
|
||||
system.membus.pkt_count::total 13965
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22364
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 9705
|
||||
system.membus.pkt_size::total 32069
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 6983
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 6983 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 6983
|
||||
system.membus.reqLayer0.occupancy 7656000
|
||||
system.membus.reqLayer0.utilization 2.0
|
||||
system.membus.respLayer0.occupancy 12691750
|
||||
system.membus.respLayer0.utilization 3.3
|
||||
system.membus.respLayer1.occupancy 2300750
|
||||
system.membus.respLayer1.utilization 0.6
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,439 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.mem_ctrl
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[1]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
children=voltage_domain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.clk_domain.voltage_domain
|
||||
|
||||
[system.clk_domain.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=-1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=65536
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.l2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=65536
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=16384
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.l2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=16384
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=SparcISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=tests/test-progs/hello/bin/sparc/linux/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.l2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.l2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.l2bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=262144
|
||||
tag_latency=20
|
||||
|
||||
[system.mem_ctrl]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:536870911:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.mem_ctrl.port
|
||||
slave=system.l2cache.mem_side system.system_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
@@ -1,13 +0,0 @@
|
||||
Redirecting stdout to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level/simout
|
||||
Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 18:41:19
|
||||
gem5 started Apr 3 2017 18:43:32
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66465
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Beginning simulation!
|
||||
Hello World!Exiting @ tick 56511000 because exiting with last active thread context
|
||||
@@ -1,716 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000057
|
||||
sim_ticks 56511000
|
||||
final_tick 56511000
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 336003
|
||||
host_op_rate 335612
|
||||
host_tick_rate 3415114336
|
||||
host_mem_usage 648892
|
||||
host_seconds 0.02
|
||||
sim_insts 5548
|
||||
sim_ops 5548
|
||||
system.clk_domain.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000
|
||||
system.mem_ctrl.bytes_read::cpu.inst 16448
|
||||
system.mem_ctrl.bytes_read::cpu.data 8768
|
||||
system.mem_ctrl.bytes_read::total 25216
|
||||
system.mem_ctrl.bytes_inst_read::cpu.inst 16448
|
||||
system.mem_ctrl.bytes_inst_read::total 16448
|
||||
system.mem_ctrl.num_reads::cpu.inst 257
|
||||
system.mem_ctrl.num_reads::cpu.data 137
|
||||
system.mem_ctrl.num_reads::total 394
|
||||
system.mem_ctrl.bw_read::cpu.inst 291058378
|
||||
system.mem_ctrl.bw_read::cpu.data 155155633
|
||||
system.mem_ctrl.bw_read::total 446214011
|
||||
system.mem_ctrl.bw_inst_read::cpu.inst 291058378
|
||||
system.mem_ctrl.bw_inst_read::total 291058378
|
||||
system.mem_ctrl.bw_total::cpu.inst 291058378
|
||||
system.mem_ctrl.bw_total::cpu.data 155155633
|
||||
system.mem_ctrl.bw_total::total 446214011
|
||||
system.mem_ctrl.readReqs 394
|
||||
system.mem_ctrl.writeReqs 0
|
||||
system.mem_ctrl.readBursts 394
|
||||
system.mem_ctrl.writeBursts 0
|
||||
system.mem_ctrl.bytesReadDRAM 25216
|
||||
system.mem_ctrl.bytesReadWrQ 0
|
||||
system.mem_ctrl.bytesWritten 0
|
||||
system.mem_ctrl.bytesReadSys 25216
|
||||
system.mem_ctrl.bytesWrittenSys 0
|
||||
system.mem_ctrl.servicedByWrQ 0
|
||||
system.mem_ctrl.mergedWrBursts 0
|
||||
system.mem_ctrl.neitherReadNorWriteReqs 0
|
||||
system.mem_ctrl.perBankRdBursts::0 21
|
||||
system.mem_ctrl.perBankRdBursts::1 7
|
||||
system.mem_ctrl.perBankRdBursts::2 1
|
||||
system.mem_ctrl.perBankRdBursts::3 7
|
||||
system.mem_ctrl.perBankRdBursts::4 0
|
||||
system.mem_ctrl.perBankRdBursts::5 69
|
||||
system.mem_ctrl.perBankRdBursts::6 79
|
||||
system.mem_ctrl.perBankRdBursts::7 62
|
||||
system.mem_ctrl.perBankRdBursts::8 32
|
||||
system.mem_ctrl.perBankRdBursts::9 17
|
||||
system.mem_ctrl.perBankRdBursts::10 9
|
||||
system.mem_ctrl.perBankRdBursts::11 47
|
||||
system.mem_ctrl.perBankRdBursts::12 10
|
||||
system.mem_ctrl.perBankRdBursts::13 21
|
||||
system.mem_ctrl.perBankRdBursts::14 5
|
||||
system.mem_ctrl.perBankRdBursts::15 7
|
||||
system.mem_ctrl.perBankWrBursts::0 0
|
||||
system.mem_ctrl.perBankWrBursts::1 0
|
||||
system.mem_ctrl.perBankWrBursts::2 0
|
||||
system.mem_ctrl.perBankWrBursts::3 0
|
||||
system.mem_ctrl.perBankWrBursts::4 0
|
||||
system.mem_ctrl.perBankWrBursts::5 0
|
||||
system.mem_ctrl.perBankWrBursts::6 0
|
||||
system.mem_ctrl.perBankWrBursts::7 0
|
||||
system.mem_ctrl.perBankWrBursts::8 0
|
||||
system.mem_ctrl.perBankWrBursts::9 0
|
||||
system.mem_ctrl.perBankWrBursts::10 0
|
||||
system.mem_ctrl.perBankWrBursts::11 0
|
||||
system.mem_ctrl.perBankWrBursts::12 0
|
||||
system.mem_ctrl.perBankWrBursts::13 0
|
||||
system.mem_ctrl.perBankWrBursts::14 0
|
||||
system.mem_ctrl.perBankWrBursts::15 0
|
||||
system.mem_ctrl.numRdRetry 0
|
||||
system.mem_ctrl.numWrRetry 0
|
||||
system.mem_ctrl.totGap 56394000
|
||||
system.mem_ctrl.readPktSize::0 0
|
||||
system.mem_ctrl.readPktSize::1 0
|
||||
system.mem_ctrl.readPktSize::2 0
|
||||
system.mem_ctrl.readPktSize::3 0
|
||||
system.mem_ctrl.readPktSize::4 0
|
||||
system.mem_ctrl.readPktSize::5 0
|
||||
system.mem_ctrl.readPktSize::6 394
|
||||
system.mem_ctrl.writePktSize::0 0
|
||||
system.mem_ctrl.writePktSize::1 0
|
||||
system.mem_ctrl.writePktSize::2 0
|
||||
system.mem_ctrl.writePktSize::3 0
|
||||
system.mem_ctrl.writePktSize::4 0
|
||||
system.mem_ctrl.writePktSize::5 0
|
||||
system.mem_ctrl.writePktSize::6 0
|
||||
system.mem_ctrl.rdQLenPdf::0 394
|
||||
system.mem_ctrl.rdQLenPdf::1 0
|
||||
system.mem_ctrl.rdQLenPdf::2 0
|
||||
system.mem_ctrl.rdQLenPdf::3 0
|
||||
system.mem_ctrl.rdQLenPdf::4 0
|
||||
system.mem_ctrl.rdQLenPdf::5 0
|
||||
system.mem_ctrl.rdQLenPdf::6 0
|
||||
system.mem_ctrl.rdQLenPdf::7 0
|
||||
system.mem_ctrl.rdQLenPdf::8 0
|
||||
system.mem_ctrl.rdQLenPdf::9 0
|
||||
system.mem_ctrl.rdQLenPdf::10 0
|
||||
system.mem_ctrl.rdQLenPdf::11 0
|
||||
system.mem_ctrl.rdQLenPdf::12 0
|
||||
system.mem_ctrl.rdQLenPdf::13 0
|
||||
system.mem_ctrl.rdQLenPdf::14 0
|
||||
system.mem_ctrl.rdQLenPdf::15 0
|
||||
system.mem_ctrl.rdQLenPdf::16 0
|
||||
system.mem_ctrl.rdQLenPdf::17 0
|
||||
system.mem_ctrl.rdQLenPdf::18 0
|
||||
system.mem_ctrl.rdQLenPdf::19 0
|
||||
system.mem_ctrl.rdQLenPdf::20 0
|
||||
system.mem_ctrl.rdQLenPdf::21 0
|
||||
system.mem_ctrl.rdQLenPdf::22 0
|
||||
system.mem_ctrl.rdQLenPdf::23 0
|
||||
system.mem_ctrl.rdQLenPdf::24 0
|
||||
system.mem_ctrl.rdQLenPdf::25 0
|
||||
system.mem_ctrl.rdQLenPdf::26 0
|
||||
system.mem_ctrl.rdQLenPdf::27 0
|
||||
system.mem_ctrl.rdQLenPdf::28 0
|
||||
system.mem_ctrl.rdQLenPdf::29 0
|
||||
system.mem_ctrl.rdQLenPdf::30 0
|
||||
system.mem_ctrl.rdQLenPdf::31 0
|
||||
system.mem_ctrl.wrQLenPdf::0 0
|
||||
system.mem_ctrl.wrQLenPdf::1 0
|
||||
system.mem_ctrl.wrQLenPdf::2 0
|
||||
system.mem_ctrl.wrQLenPdf::3 0
|
||||
system.mem_ctrl.wrQLenPdf::4 0
|
||||
system.mem_ctrl.wrQLenPdf::5 0
|
||||
system.mem_ctrl.wrQLenPdf::6 0
|
||||
system.mem_ctrl.wrQLenPdf::7 0
|
||||
system.mem_ctrl.wrQLenPdf::8 0
|
||||
system.mem_ctrl.wrQLenPdf::9 0
|
||||
system.mem_ctrl.wrQLenPdf::10 0
|
||||
system.mem_ctrl.wrQLenPdf::11 0
|
||||
system.mem_ctrl.wrQLenPdf::12 0
|
||||
system.mem_ctrl.wrQLenPdf::13 0
|
||||
system.mem_ctrl.wrQLenPdf::14 0
|
||||
system.mem_ctrl.wrQLenPdf::15 0
|
||||
system.mem_ctrl.wrQLenPdf::16 0
|
||||
system.mem_ctrl.wrQLenPdf::17 0
|
||||
system.mem_ctrl.wrQLenPdf::18 0
|
||||
system.mem_ctrl.wrQLenPdf::19 0
|
||||
system.mem_ctrl.wrQLenPdf::20 0
|
||||
system.mem_ctrl.wrQLenPdf::21 0
|
||||
system.mem_ctrl.wrQLenPdf::22 0
|
||||
system.mem_ctrl.wrQLenPdf::23 0
|
||||
system.mem_ctrl.wrQLenPdf::24 0
|
||||
system.mem_ctrl.wrQLenPdf::25 0
|
||||
system.mem_ctrl.wrQLenPdf::26 0
|
||||
system.mem_ctrl.wrQLenPdf::27 0
|
||||
system.mem_ctrl.wrQLenPdf::28 0
|
||||
system.mem_ctrl.wrQLenPdf::29 0
|
||||
system.mem_ctrl.wrQLenPdf::30 0
|
||||
system.mem_ctrl.wrQLenPdf::31 0
|
||||
system.mem_ctrl.wrQLenPdf::32 0
|
||||
system.mem_ctrl.wrQLenPdf::33 0
|
||||
system.mem_ctrl.wrQLenPdf::34 0
|
||||
system.mem_ctrl.wrQLenPdf::35 0
|
||||
system.mem_ctrl.wrQLenPdf::36 0
|
||||
system.mem_ctrl.wrQLenPdf::37 0
|
||||
system.mem_ctrl.wrQLenPdf::38 0
|
||||
system.mem_ctrl.wrQLenPdf::39 0
|
||||
system.mem_ctrl.wrQLenPdf::40 0
|
||||
system.mem_ctrl.wrQLenPdf::41 0
|
||||
system.mem_ctrl.wrQLenPdf::42 0
|
||||
system.mem_ctrl.wrQLenPdf::43 0
|
||||
system.mem_ctrl.wrQLenPdf::44 0
|
||||
system.mem_ctrl.wrQLenPdf::45 0
|
||||
system.mem_ctrl.wrQLenPdf::46 0
|
||||
system.mem_ctrl.wrQLenPdf::47 0
|
||||
system.mem_ctrl.wrQLenPdf::48 0
|
||||
system.mem_ctrl.wrQLenPdf::49 0
|
||||
system.mem_ctrl.wrQLenPdf::50 0
|
||||
system.mem_ctrl.wrQLenPdf::51 0
|
||||
system.mem_ctrl.wrQLenPdf::52 0
|
||||
system.mem_ctrl.wrQLenPdf::53 0
|
||||
system.mem_ctrl.wrQLenPdf::54 0
|
||||
system.mem_ctrl.wrQLenPdf::55 0
|
||||
system.mem_ctrl.wrQLenPdf::56 0
|
||||
system.mem_ctrl.wrQLenPdf::57 0
|
||||
system.mem_ctrl.wrQLenPdf::58 0
|
||||
system.mem_ctrl.wrQLenPdf::59 0
|
||||
system.mem_ctrl.wrQLenPdf::60 0
|
||||
system.mem_ctrl.wrQLenPdf::61 0
|
||||
system.mem_ctrl.wrQLenPdf::62 0
|
||||
system.mem_ctrl.wrQLenPdf::63 0
|
||||
system.mem_ctrl.bytesPerActivate::samples 98
|
||||
system.mem_ctrl.bytesPerActivate::mean 248.816327
|
||||
system.mem_ctrl.bytesPerActivate::gmean 183.748429
|
||||
system.mem_ctrl.bytesPerActivate::stdev 196.431638
|
||||
system.mem_ctrl.bytesPerActivate::0-127 26 26.53% 26.53%
|
||||
system.mem_ctrl.bytesPerActivate::128-255 31 31.63% 58.16%
|
||||
system.mem_ctrl.bytesPerActivate::256-383 15 15.31% 73.47%
|
||||
system.mem_ctrl.bytesPerActivate::384-511 13 13.27% 86.73%
|
||||
system.mem_ctrl.bytesPerActivate::512-639 9 9.18% 95.92%
|
||||
system.mem_ctrl.bytesPerActivate::640-767 2 2.04% 97.96%
|
||||
system.mem_ctrl.bytesPerActivate::896-1023 1 1.02% 98.98%
|
||||
system.mem_ctrl.bytesPerActivate::1024-1151 1 1.02% 100.00%
|
||||
system.mem_ctrl.bytesPerActivate::total 98
|
||||
system.mem_ctrl.totQLat 5793000
|
||||
system.mem_ctrl.totMemAccLat 13180500
|
||||
system.mem_ctrl.totBusLat 1970000
|
||||
system.mem_ctrl.avgQLat 14703.05
|
||||
system.mem_ctrl.avgBusLat 5000.00
|
||||
system.mem_ctrl.avgMemAccLat 33453.05
|
||||
system.mem_ctrl.avgRdBW 446.21
|
||||
system.mem_ctrl.avgWrBW 0.00
|
||||
system.mem_ctrl.avgRdBWSys 446.21
|
||||
system.mem_ctrl.avgWrBWSys 0.00
|
||||
system.mem_ctrl.peakBW 12800.00
|
||||
system.mem_ctrl.busUtil 3.49
|
||||
system.mem_ctrl.busUtilRead 3.49
|
||||
system.mem_ctrl.busUtilWrite 0.00
|
||||
system.mem_ctrl.avgRdQLen 1.00
|
||||
system.mem_ctrl.avgWrQLen 0.00
|
||||
system.mem_ctrl.readRowHits 292
|
||||
system.mem_ctrl.writeRowHits 0
|
||||
system.mem_ctrl.readRowHitRate 74.11
|
||||
system.mem_ctrl.writeRowHitRate nan
|
||||
system.mem_ctrl.avgGap 143131.98
|
||||
system.mem_ctrl.pageHitRate 74.11
|
||||
system.mem_ctrl_0.actEnergy 421260
|
||||
system.mem_ctrl_0.preEnergy 216315
|
||||
system.mem_ctrl_0.readEnergy 1756440
|
||||
system.mem_ctrl_0.writeEnergy 0
|
||||
system.mem_ctrl_0.refreshEnergy 4302480.000000
|
||||
system.mem_ctrl_0.actBackEnergy 4075500
|
||||
system.mem_ctrl_0.preBackEnergy 122880
|
||||
system.mem_ctrl_0.actPowerDownEnergy 21123630
|
||||
system.mem_ctrl_0.prePowerDownEnergy 357120
|
||||
system.mem_ctrl_0.selfRefreshEnergy 0
|
||||
system.mem_ctrl_0.totalEnergy 32375625
|
||||
system.mem_ctrl_0.averagePower 572.905837
|
||||
system.mem_ctrl_0.totalIdleTime 47002000
|
||||
system.mem_ctrl_0.memoryStateTime::IDLE 71000
|
||||
system.mem_ctrl_0.memoryStateTime::REF 1820000
|
||||
system.mem_ctrl_0.memoryStateTime::SREF 0
|
||||
system.mem_ctrl_0.memoryStateTime::PRE_PDN 929250
|
||||
system.mem_ctrl_0.memoryStateTime::ACT 7357750
|
||||
system.mem_ctrl_0.memoryStateTime::ACT_PDN 46333000
|
||||
system.mem_ctrl_1.actEnergy 307020
|
||||
system.mem_ctrl_1.preEnergy 155595
|
||||
system.mem_ctrl_1.readEnergy 1056720
|
||||
system.mem_ctrl_1.writeEnergy 0
|
||||
system.mem_ctrl_1.refreshEnergy 4302480.000000
|
||||
system.mem_ctrl_1.actBackEnergy 2785590
|
||||
system.mem_ctrl_1.preBackEnergy 293760
|
||||
system.mem_ctrl_1.actPowerDownEnergy 20523420
|
||||
system.mem_ctrl_1.prePowerDownEnergy 1777920
|
||||
system.mem_ctrl_1.selfRefreshEnergy 0
|
||||
system.mem_ctrl_1.totalEnergy 31202505
|
||||
system.mem_ctrl_1.averagePower 552.146785
|
||||
system.mem_ctrl_1.totalIdleTime 49582750
|
||||
system.mem_ctrl_1.memoryStateTime::IDLE 557000
|
||||
system.mem_ctrl_1.memoryStateTime::REF 1820000
|
||||
system.mem_ctrl_1.memoryStateTime::SREF 0
|
||||
system.mem_ctrl_1.memoryStateTime::PRE_PDN 4629500
|
||||
system.mem_ctrl_1.memoryStateTime::ACT 4495750
|
||||
system.mem_ctrl_1.memoryStateTime::ACT_PDN 45008750
|
||||
system.pwrStateResidencyTicks::UNDEFINED 56511000
|
||||
system.cpu.workload.numSyscalls 11
|
||||
system.cpu.pwrStateResidencyTicks::ON 56511000
|
||||
system.cpu.numCycles 56511
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 5548
|
||||
system.cpu.committedOps 5548
|
||||
system.cpu.num_int_alu_accesses 4660
|
||||
system.cpu.num_fp_alu_accesses 0
|
||||
system.cpu.num_func_calls 146
|
||||
system.cpu.num_conditional_control_insts 835
|
||||
system.cpu.num_int_insts 4660
|
||||
system.cpu.num_fp_insts 0
|
||||
system.cpu.num_int_register_reads 10977
|
||||
system.cpu.num_int_register_writes 5062
|
||||
system.cpu.num_fp_register_reads 0
|
||||
system.cpu.num_fp_register_writes 0
|
||||
system.cpu.num_mem_refs 1404
|
||||
system.cpu.num_load_insts 726
|
||||
system.cpu.num_store_insts 678
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 56511
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 1187
|
||||
system.cpu.op_class::No_OpClass 173 3.09% 3.09%
|
||||
system.cpu.op_class::IntAlu 4014 71.79% 74.89%
|
||||
system.cpu.op_class::IntMult 0 0.00% 74.89%
|
||||
system.cpu.op_class::IntDiv 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 74.89%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89%
|
||||
system.cpu.op_class::MemRead 726 12.99% 87.87%
|
||||
system.cpu.op_class::MemWrite 678 12.13% 100.00%
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
|
||||
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 5591
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56511000
|
||||
system.cpu.dcache.tags.replacements 0
|
||||
system.cpu.dcache.tags.tagsinuse 83.847801
|
||||
system.cpu.dcache.tags.total_refs 1253
|
||||
system.cpu.dcache.tags.sampled_refs 138
|
||||
system.cpu.dcache.tags.avg_refs 9.079710
|
||||
system.cpu.dcache.tags.warmup_cycle 0
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 83.847801
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.081883
|
||||
system.cpu.dcache.tags.occ_percent::total 0.081883
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 138
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 10
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 128
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766
|
||||
system.cpu.dcache.tags.tag_accesses 2920
|
||||
system.cpu.dcache.tags.data_accesses 2920
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56511000
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 662
|
||||
system.cpu.dcache.ReadReq_hits::total 662
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 591
|
||||
system.cpu.dcache.WriteReq_hits::total 591
|
||||
system.cpu.dcache.demand_hits::cpu.data 1253
|
||||
system.cpu.dcache.demand_hits::total 1253
|
||||
system.cpu.dcache.overall_hits::cpu.data 1253
|
||||
system.cpu.dcache.overall_hits::total 1253
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 56
|
||||
system.cpu.dcache.ReadReq_misses::total 56
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 82
|
||||
system.cpu.dcache.WriteReq_misses::total 82
|
||||
system.cpu.dcache.demand_misses::cpu.data 138
|
||||
system.cpu.dcache.demand_misses::total 138
|
||||
system.cpu.dcache.overall_misses::cpu.data 138
|
||||
system.cpu.dcache.overall_misses::total 138
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6576000
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6576000
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8937000
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8937000
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 15513000
|
||||
system.cpu.dcache.demand_miss_latency::total 15513000
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 15513000
|
||||
system.cpu.dcache.overall_miss_latency::total 15513000
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 718
|
||||
system.cpu.dcache.ReadReq_accesses::total 718
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 673
|
||||
system.cpu.dcache.WriteReq_accesses::total 673
|
||||
system.cpu.dcache.demand_accesses::cpu.data 1391
|
||||
system.cpu.dcache.demand_accesses::total 1391
|
||||
system.cpu.dcache.overall_accesses::cpu.data 1391
|
||||
system.cpu.dcache.overall_accesses::total 1391
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.077994
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.121842
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.099209
|
||||
system.cpu.dcache.demand_miss_rate::total 0.099209
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.099209
|
||||
system.cpu.dcache.overall_miss_rate::total 0.099209
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 117428.571429
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 117428.571429
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108987.804878
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 108987.804878
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 112413.043478
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 112413.043478
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 112413.043478
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 112413.043478
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0
|
||||
system.cpu.dcache.blocked::no_mshrs 0
|
||||
system.cpu.dcache.blocked::no_targets 0
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 56
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 82
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
||||
system.cpu.dcache.demand_mshr_misses::total 138
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138
|
||||
system.cpu.dcache.overall_mshr_misses::total 138
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6464000
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6464000
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8773000
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8773000
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15237000
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 15237000
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15237000
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 15237000
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.099209
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.099209
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115428.571429
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115428.571429
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106987.804878
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106987.804878
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 110413.043478
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 110413.043478
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 110413.043478
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 110413.043478
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56511000
|
||||
system.cpu.icache.tags.replacements 71
|
||||
system.cpu.icache.tags.tagsinuse 98.324434
|
||||
system.cpu.icache.tags.total_refs 5333
|
||||
system.cpu.icache.tags.sampled_refs 259
|
||||
system.cpu.icache.tags.avg_refs 20.590734
|
||||
system.cpu.icache.tags.warmup_cycle 0
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 98.324434
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.384080
|
||||
system.cpu.icache.tags.occ_percent::total 0.384080
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 188
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 54
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 134
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.734375
|
||||
system.cpu.icache.tags.tag_accesses 11443
|
||||
system.cpu.icache.tags.data_accesses 11443
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56511000
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 5333
|
||||
system.cpu.icache.ReadReq_hits::total 5333
|
||||
system.cpu.icache.demand_hits::cpu.inst 5333
|
||||
system.cpu.icache.demand_hits::total 5333
|
||||
system.cpu.icache.overall_hits::cpu.inst 5333
|
||||
system.cpu.icache.overall_hits::total 5333
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 259
|
||||
system.cpu.icache.ReadReq_misses::total 259
|
||||
system.cpu.icache.demand_misses::cpu.inst 259
|
||||
system.cpu.icache.demand_misses::total 259
|
||||
system.cpu.icache.overall_misses::cpu.inst 259
|
||||
system.cpu.icache.overall_misses::total 259
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 27828000
|
||||
system.cpu.icache.ReadReq_miss_latency::total 27828000
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 27828000
|
||||
system.cpu.icache.demand_miss_latency::total 27828000
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 27828000
|
||||
system.cpu.icache.overall_miss_latency::total 27828000
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5592
|
||||
system.cpu.icache.ReadReq_accesses::total 5592
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5592
|
||||
system.cpu.icache.demand_accesses::total 5592
|
||||
system.cpu.icache.overall_accesses::cpu.inst 5592
|
||||
system.cpu.icache.overall_accesses::total 5592
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.046316
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.046316
|
||||
system.cpu.icache.demand_miss_rate::total 0.046316
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.046316
|
||||
system.cpu.icache.overall_miss_rate::total 0.046316
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 107444.015444
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 107444.015444
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 107444.015444
|
||||
system.cpu.icache.demand_avg_miss_latency::total 107444.015444
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 107444.015444
|
||||
system.cpu.icache.overall_avg_miss_latency::total 107444.015444
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.icache.blocked_cycles::no_targets 0
|
||||
system.cpu.icache.blocked::no_mshrs 0
|
||||
system.cpu.icache.blocked::no_targets 0
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 259
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 259
|
||||
system.cpu.icache.demand_mshr_misses::total 259
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 259
|
||||
system.cpu.icache.overall_mshr_misses::total 259
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27310000
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 27310000
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27310000
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 27310000
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27310000
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 27310000
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.046316
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.046316
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 105444.015444
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 105444.015444
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 105444.015444
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 105444.015444
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 105444.015444
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 105444.015444
|
||||
system.l2bus.snoop_filter.tot_requests 468
|
||||
system.l2bus.snoop_filter.hit_single_requests 73
|
||||
system.l2bus.snoop_filter.hit_multi_requests 1
|
||||
system.l2bus.snoop_filter.tot_snoops 0
|
||||
system.l2bus.snoop_filter.hit_single_snoops 0
|
||||
system.l2bus.snoop_filter.hit_multi_snoops 0
|
||||
system.l2bus.pwrStateResidencyTicks::UNDEFINED 56511000
|
||||
system.l2bus.trans_dist::ReadResp 315
|
||||
system.l2bus.trans_dist::CleanEvict 71
|
||||
system.l2bus.trans_dist::ReadExReq 82
|
||||
system.l2bus.trans_dist::ReadExResp 82
|
||||
system.l2bus.trans_dist::ReadSharedReq 315
|
||||
system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589
|
||||
system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276
|
||||
system.l2bus.pkt_count::total 865
|
||||
system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 16576
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832
|
||||
system.l2bus.pkt_size::total 25408
|
||||
system.l2bus.snoops 0
|
||||
system.l2bus.snoopTraffic 0
|
||||
system.l2bus.snoop_fanout::samples 397
|
||||
system.l2bus.snoop_fanout::mean 0.007557
|
||||
system.l2bus.snoop_fanout::stdev 0.086709
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.l2bus.snoop_fanout::0 394 99.24% 99.24%
|
||||
system.l2bus.snoop_fanout::1 3 0.76% 100.00%
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00%
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.l2bus.snoop_fanout::min_value 0
|
||||
system.l2bus.snoop_fanout::max_value 1
|
||||
system.l2bus.snoop_fanout::total 397
|
||||
system.l2bus.reqLayer0.occupancy 468000
|
||||
system.l2bus.reqLayer0.utilization 0.8
|
||||
system.l2bus.respLayer0.occupancy 777000
|
||||
system.l2bus.respLayer0.utilization 1.4
|
||||
system.l2bus.respLayer1.occupancy 414000
|
||||
system.l2bus.respLayer1.utilization 0.7
|
||||
system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56511000
|
||||
system.l2cache.tags.replacements 0
|
||||
system.l2cache.tags.tagsinuse 201.052259
|
||||
system.l2cache.tags.total_refs 73
|
||||
system.l2cache.tags.sampled_refs 394
|
||||
system.l2cache.tags.avg_refs 0.185279
|
||||
system.l2cache.tags.warmup_cycle 0
|
||||
system.l2cache.tags.occ_blocks::cpu.inst 118.133782
|
||||
system.l2cache.tags.occ_blocks::cpu.data 82.918477
|
||||
system.l2cache.tags.occ_percent::cpu.inst 0.028841
|
||||
system.l2cache.tags.occ_percent::cpu.data 0.020244
|
||||
system.l2cache.tags.occ_percent::total 0.049085
|
||||
system.l2cache.tags.occ_task_id_blocks::1024 394
|
||||
system.l2cache.tags.age_task_id_blocks_1024::0 62
|
||||
system.l2cache.tags.age_task_id_blocks_1024::1 332
|
||||
system.l2cache.tags.occ_task_id_percent::1024 0.096191
|
||||
system.l2cache.tags.tag_accesses 4130
|
||||
system.l2cache.tags.data_accesses 4130
|
||||
system.l2cache.pwrStateResidencyTicks::UNDEFINED 56511000
|
||||
system.l2cache.ReadSharedReq_hits::cpu.inst 2
|
||||
system.l2cache.ReadSharedReq_hits::cpu.data 1
|
||||
system.l2cache.ReadSharedReq_hits::total 3
|
||||
system.l2cache.demand_hits::cpu.inst 2
|
||||
system.l2cache.demand_hits::cpu.data 1
|
||||
system.l2cache.demand_hits::total 3
|
||||
system.l2cache.overall_hits::cpu.inst 2
|
||||
system.l2cache.overall_hits::cpu.data 1
|
||||
system.l2cache.overall_hits::total 3
|
||||
system.l2cache.ReadExReq_misses::cpu.data 82
|
||||
system.l2cache.ReadExReq_misses::total 82
|
||||
system.l2cache.ReadSharedReq_misses::cpu.inst 257
|
||||
system.l2cache.ReadSharedReq_misses::cpu.data 55
|
||||
system.l2cache.ReadSharedReq_misses::total 312
|
||||
system.l2cache.demand_misses::cpu.inst 257
|
||||
system.l2cache.demand_misses::cpu.data 137
|
||||
system.l2cache.demand_misses::total 394
|
||||
system.l2cache.overall_misses::cpu.inst 257
|
||||
system.l2cache.overall_misses::cpu.data 137
|
||||
system.l2cache.overall_misses::total 394
|
||||
system.l2cache.ReadExReq_miss_latency::cpu.data 8527000
|
||||
system.l2cache.ReadExReq_miss_latency::total 8527000
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26487000
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.data 6273000
|
||||
system.l2cache.ReadSharedReq_miss_latency::total 32760000
|
||||
system.l2cache.demand_miss_latency::cpu.inst 26487000
|
||||
system.l2cache.demand_miss_latency::cpu.data 14800000
|
||||
system.l2cache.demand_miss_latency::total 41287000
|
||||
system.l2cache.overall_miss_latency::cpu.inst 26487000
|
||||
system.l2cache.overall_miss_latency::cpu.data 14800000
|
||||
system.l2cache.overall_miss_latency::total 41287000
|
||||
system.l2cache.ReadExReq_accesses::cpu.data 82
|
||||
system.l2cache.ReadExReq_accesses::total 82
|
||||
system.l2cache.ReadSharedReq_accesses::cpu.inst 259
|
||||
system.l2cache.ReadSharedReq_accesses::cpu.data 56
|
||||
system.l2cache.ReadSharedReq_accesses::total 315
|
||||
system.l2cache.demand_accesses::cpu.inst 259
|
||||
system.l2cache.demand_accesses::cpu.data 138
|
||||
system.l2cache.demand_accesses::total 397
|
||||
system.l2cache.overall_accesses::cpu.inst 259
|
||||
system.l2cache.overall_accesses::cpu.data 138
|
||||
system.l2cache.overall_accesses::total 397
|
||||
system.l2cache.ReadExReq_miss_rate::cpu.data 1
|
||||
system.l2cache.ReadExReq_miss_rate::total 1
|
||||
system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.992278
|
||||
system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143
|
||||
system.l2cache.ReadSharedReq_miss_rate::total 0.990476
|
||||
system.l2cache.demand_miss_rate::cpu.inst 0.992278
|
||||
system.l2cache.demand_miss_rate::cpu.data 0.992754
|
||||
system.l2cache.demand_miss_rate::total 0.992443
|
||||
system.l2cache.overall_miss_rate::cpu.inst 0.992278
|
||||
system.l2cache.overall_miss_rate::cpu.data 0.992754
|
||||
system.l2cache.overall_miss_rate::total 0.992443
|
||||
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103987.804878
|
||||
system.l2cache.ReadExReq_avg_miss_latency::total 103987.804878
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 103062.256809
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 114054.545455
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::total 105000
|
||||
system.l2cache.demand_avg_miss_latency::cpu.inst 103062.256809
|
||||
system.l2cache.demand_avg_miss_latency::cpu.data 108029.197080
|
||||
system.l2cache.demand_avg_miss_latency::total 104789.340102
|
||||
system.l2cache.overall_avg_miss_latency::cpu.inst 103062.256809
|
||||
system.l2cache.overall_avg_miss_latency::cpu.data 108029.197080
|
||||
system.l2cache.overall_avg_miss_latency::total 104789.340102
|
||||
system.l2cache.blocked_cycles::no_mshrs 0
|
||||
system.l2cache.blocked_cycles::no_targets 0
|
||||
system.l2cache.blocked::no_mshrs 0
|
||||
system.l2cache.blocked::no_targets 0
|
||||
system.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.l2cache.avg_blocked_cycles::no_targets nan
|
||||
system.l2cache.ReadExReq_mshr_misses::cpu.data 82
|
||||
system.l2cache.ReadExReq_mshr_misses::total 82
|
||||
system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257
|
||||
system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55
|
||||
system.l2cache.ReadSharedReq_mshr_misses::total 312
|
||||
system.l2cache.demand_mshr_misses::cpu.inst 257
|
||||
system.l2cache.demand_mshr_misses::cpu.data 137
|
||||
system.l2cache.demand_mshr_misses::total 394
|
||||
system.l2cache.overall_mshr_misses::cpu.inst 257
|
||||
system.l2cache.overall_mshr_misses::cpu.data 137
|
||||
system.l2cache.overall_mshr_misses::total 394
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6887000
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::total 6887000
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21347000
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5173000
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::total 26520000
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.inst 21347000
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.data 12060000
|
||||
system.l2cache.demand_mshr_miss_latency::total 33407000
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.inst 21347000
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.data 12060000
|
||||
system.l2cache.overall_mshr_miss_latency::total 33407000
|
||||
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
|
||||
system.l2cache.ReadExReq_mshr_miss_rate::total 1
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476
|
||||
system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278
|
||||
system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754
|
||||
system.l2cache.demand_mshr_miss_rate::total 0.992443
|
||||
system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278
|
||||
system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754
|
||||
system.l2cache.overall_mshr_miss_rate::total 0.992443
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83987.804878
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83987.804878
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 83062.256809
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 94054.545455
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85000
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83062.256809
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 88029.197080
|
||||
system.l2cache.demand_avg_mshr_miss_latency::total 84789.340102
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83062.256809
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 88029.197080
|
||||
system.l2cache.overall_avg_mshr_miss_latency::total 84789.340102
|
||||
system.membus.snoop_filter.tot_requests 394
|
||||
system.membus.snoop_filter.hit_single_requests 0
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 56511000
|
||||
system.membus.trans_dist::ReadResp 312
|
||||
system.membus.trans_dist::ReadExReq 82
|
||||
system.membus.trans_dist::ReadExResp 82
|
||||
system.membus.trans_dist::ReadSharedReq 312
|
||||
system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788
|
||||
system.membus.pkt_count::total 788
|
||||
system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216
|
||||
system.membus.pkt_size::total 25216
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 394
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 394 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 394
|
||||
system.membus.reqLayer0.occupancy 394000
|
||||
system.membus.reqLayer0.utilization 0.7
|
||||
system.membus.respLayer0.occupancy 2102500
|
||||
system.membus.respLayer0.utilization 3.7
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,314 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler mem_ctrl membus
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kvm_vm=Null
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.mem_ctrl
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[3]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
children=voltage_domain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.clk_domain.voltage_domain
|
||||
|
||||
[system.clk_domain.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=apic_clk_domain dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=-1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[1]
|
||||
icache_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[1]
|
||||
pio=system.membus.master[0]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=tests/test-progs/hello/bin/x86/linux/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.mem_ctrl]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:536870911:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port
|
||||
slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.interrupts.int_master system.system_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
@@ -1,14 +0,0 @@
|
||||
Redirecting stdout to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple/simout
|
||||
Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 19:05:53
|
||||
gem5 started Apr 3 2017 19:06:23
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87205
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Beginning simulation!
|
||||
Hello world!
|
||||
Exiting @ tick 507841000 because exiting with last active thread context
|
||||
@@ -1,398 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000508
|
||||
sim_ticks 507841000
|
||||
final_tick 507841000
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 110016
|
||||
host_op_rate 198569
|
||||
host_tick_rate 9773316243
|
||||
host_mem_usage 663056
|
||||
host_seconds 0.05
|
||||
sim_insts 5712
|
||||
sim_ops 10314
|
||||
system.clk_domain.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000
|
||||
system.mem_ctrl.bytes_read::cpu.inst 58264
|
||||
system.mem_ctrl.bytes_read::cpu.data 7167
|
||||
system.mem_ctrl.bytes_read::total 65431
|
||||
system.mem_ctrl.bytes_inst_read::cpu.inst 58264
|
||||
system.mem_ctrl.bytes_inst_read::total 58264
|
||||
system.mem_ctrl.bytes_written::cpu.data 7160
|
||||
system.mem_ctrl.bytes_written::total 7160
|
||||
system.mem_ctrl.num_reads::cpu.inst 7283
|
||||
system.mem_ctrl.num_reads::cpu.data 1084
|
||||
system.mem_ctrl.num_reads::total 8367
|
||||
system.mem_ctrl.num_writes::cpu.data 941
|
||||
system.mem_ctrl.num_writes::total 941
|
||||
system.mem_ctrl.bw_read::cpu.inst 114728823
|
||||
system.mem_ctrl.bw_read::cpu.data 14112685
|
||||
system.mem_ctrl.bw_read::total 128841507
|
||||
system.mem_ctrl.bw_inst_read::cpu.inst 114728823
|
||||
system.mem_ctrl.bw_inst_read::total 114728823
|
||||
system.mem_ctrl.bw_write::cpu.data 14098901
|
||||
system.mem_ctrl.bw_write::total 14098901
|
||||
system.mem_ctrl.bw_total::cpu.inst 114728823
|
||||
system.mem_ctrl.bw_total::cpu.data 28211586
|
||||
system.mem_ctrl.bw_total::total 142940409
|
||||
system.mem_ctrl.readReqs 8368
|
||||
system.mem_ctrl.writeReqs 941
|
||||
system.mem_ctrl.readBursts 8368
|
||||
system.mem_ctrl.writeBursts 941
|
||||
system.mem_ctrl.bytesReadDRAM 525248
|
||||
system.mem_ctrl.bytesReadWrQ 10304
|
||||
system.mem_ctrl.bytesWritten 7168
|
||||
system.mem_ctrl.bytesReadSys 65439
|
||||
system.mem_ctrl.bytesWrittenSys 7160
|
||||
system.mem_ctrl.servicedByWrQ 161
|
||||
system.mem_ctrl.mergedWrBursts 810
|
||||
system.mem_ctrl.neitherReadNorWriteReqs 0
|
||||
system.mem_ctrl.perBankRdBursts::0 277
|
||||
system.mem_ctrl.perBankRdBursts::1 4
|
||||
system.mem_ctrl.perBankRdBursts::2 227
|
||||
system.mem_ctrl.perBankRdBursts::3 102
|
||||
system.mem_ctrl.perBankRdBursts::4 1619
|
||||
system.mem_ctrl.perBankRdBursts::5 965
|
||||
system.mem_ctrl.perBankRdBursts::6 1103
|
||||
system.mem_ctrl.perBankRdBursts::7 906
|
||||
system.mem_ctrl.perBankRdBursts::8 703
|
||||
system.mem_ctrl.perBankRdBursts::9 491
|
||||
system.mem_ctrl.perBankRdBursts::10 1059
|
||||
system.mem_ctrl.perBankRdBursts::11 59
|
||||
system.mem_ctrl.perBankRdBursts::12 11
|
||||
system.mem_ctrl.perBankRdBursts::13 489
|
||||
system.mem_ctrl.perBankRdBursts::14 78
|
||||
system.mem_ctrl.perBankRdBursts::15 114
|
||||
system.mem_ctrl.perBankWrBursts::0 10
|
||||
system.mem_ctrl.perBankWrBursts::1 0
|
||||
system.mem_ctrl.perBankWrBursts::2 0
|
||||
system.mem_ctrl.perBankWrBursts::3 0
|
||||
system.mem_ctrl.perBankWrBursts::4 0
|
||||
system.mem_ctrl.perBankWrBursts::5 0
|
||||
system.mem_ctrl.perBankWrBursts::6 0
|
||||
system.mem_ctrl.perBankWrBursts::7 0
|
||||
system.mem_ctrl.perBankWrBursts::8 3
|
||||
system.mem_ctrl.perBankWrBursts::9 54
|
||||
system.mem_ctrl.perBankWrBursts::10 34
|
||||
system.mem_ctrl.perBankWrBursts::11 7
|
||||
system.mem_ctrl.perBankWrBursts::12 0
|
||||
system.mem_ctrl.perBankWrBursts::13 0
|
||||
system.mem_ctrl.perBankWrBursts::14 0
|
||||
system.mem_ctrl.perBankWrBursts::15 4
|
||||
system.mem_ctrl.numRdRetry 0
|
||||
system.mem_ctrl.numWrRetry 0
|
||||
system.mem_ctrl.totGap 507764000
|
||||
system.mem_ctrl.readPktSize::0 135
|
||||
system.mem_ctrl.readPktSize::1 14
|
||||
system.mem_ctrl.readPktSize::2 119
|
||||
system.mem_ctrl.readPktSize::3 8100
|
||||
system.mem_ctrl.readPktSize::4 0
|
||||
system.mem_ctrl.readPktSize::5 0
|
||||
system.mem_ctrl.readPktSize::6 0
|
||||
system.mem_ctrl.writePktSize::0 14
|
||||
system.mem_ctrl.writePktSize::1 3
|
||||
system.mem_ctrl.writePktSize::2 63
|
||||
system.mem_ctrl.writePktSize::3 861
|
||||
system.mem_ctrl.writePktSize::4 0
|
||||
system.mem_ctrl.writePktSize::5 0
|
||||
system.mem_ctrl.writePktSize::6 0
|
||||
system.mem_ctrl.rdQLenPdf::0 8207
|
||||
system.mem_ctrl.rdQLenPdf::1 0
|
||||
system.mem_ctrl.rdQLenPdf::2 0
|
||||
system.mem_ctrl.rdQLenPdf::3 0
|
||||
system.mem_ctrl.rdQLenPdf::4 0
|
||||
system.mem_ctrl.rdQLenPdf::5 0
|
||||
system.mem_ctrl.rdQLenPdf::6 0
|
||||
system.mem_ctrl.rdQLenPdf::7 0
|
||||
system.mem_ctrl.rdQLenPdf::8 0
|
||||
system.mem_ctrl.rdQLenPdf::9 0
|
||||
system.mem_ctrl.rdQLenPdf::10 0
|
||||
system.mem_ctrl.rdQLenPdf::11 0
|
||||
system.mem_ctrl.rdQLenPdf::12 0
|
||||
system.mem_ctrl.rdQLenPdf::13 0
|
||||
system.mem_ctrl.rdQLenPdf::14 0
|
||||
system.mem_ctrl.rdQLenPdf::15 0
|
||||
system.mem_ctrl.rdQLenPdf::16 0
|
||||
system.mem_ctrl.rdQLenPdf::17 0
|
||||
system.mem_ctrl.rdQLenPdf::18 0
|
||||
system.mem_ctrl.rdQLenPdf::19 0
|
||||
system.mem_ctrl.rdQLenPdf::20 0
|
||||
system.mem_ctrl.rdQLenPdf::21 0
|
||||
system.mem_ctrl.rdQLenPdf::22 0
|
||||
system.mem_ctrl.rdQLenPdf::23 0
|
||||
system.mem_ctrl.rdQLenPdf::24 0
|
||||
system.mem_ctrl.rdQLenPdf::25 0
|
||||
system.mem_ctrl.rdQLenPdf::26 0
|
||||
system.mem_ctrl.rdQLenPdf::27 0
|
||||
system.mem_ctrl.rdQLenPdf::28 0
|
||||
system.mem_ctrl.rdQLenPdf::29 0
|
||||
system.mem_ctrl.rdQLenPdf::30 0
|
||||
system.mem_ctrl.rdQLenPdf::31 0
|
||||
system.mem_ctrl.wrQLenPdf::0 1
|
||||
system.mem_ctrl.wrQLenPdf::1 1
|
||||
system.mem_ctrl.wrQLenPdf::2 1
|
||||
system.mem_ctrl.wrQLenPdf::3 1
|
||||
system.mem_ctrl.wrQLenPdf::4 1
|
||||
system.mem_ctrl.wrQLenPdf::5 1
|
||||
system.mem_ctrl.wrQLenPdf::6 1
|
||||
system.mem_ctrl.wrQLenPdf::7 1
|
||||
system.mem_ctrl.wrQLenPdf::8 1
|
||||
system.mem_ctrl.wrQLenPdf::9 1
|
||||
system.mem_ctrl.wrQLenPdf::10 1
|
||||
system.mem_ctrl.wrQLenPdf::11 1
|
||||
system.mem_ctrl.wrQLenPdf::12 1
|
||||
system.mem_ctrl.wrQLenPdf::13 1
|
||||
system.mem_ctrl.wrQLenPdf::14 1
|
||||
system.mem_ctrl.wrQLenPdf::15 1
|
||||
system.mem_ctrl.wrQLenPdf::16 1
|
||||
system.mem_ctrl.wrQLenPdf::17 8
|
||||
system.mem_ctrl.wrQLenPdf::18 8
|
||||
system.mem_ctrl.wrQLenPdf::19 7
|
||||
system.mem_ctrl.wrQLenPdf::20 7
|
||||
system.mem_ctrl.wrQLenPdf::21 7
|
||||
system.mem_ctrl.wrQLenPdf::22 7
|
||||
system.mem_ctrl.wrQLenPdf::23 7
|
||||
system.mem_ctrl.wrQLenPdf::24 7
|
||||
system.mem_ctrl.wrQLenPdf::25 7
|
||||
system.mem_ctrl.wrQLenPdf::26 7
|
||||
system.mem_ctrl.wrQLenPdf::27 7
|
||||
system.mem_ctrl.wrQLenPdf::28 7
|
||||
system.mem_ctrl.wrQLenPdf::29 7
|
||||
system.mem_ctrl.wrQLenPdf::30 7
|
||||
system.mem_ctrl.wrQLenPdf::31 7
|
||||
system.mem_ctrl.wrQLenPdf::32 7
|
||||
system.mem_ctrl.wrQLenPdf::33 0
|
||||
system.mem_ctrl.wrQLenPdf::34 0
|
||||
system.mem_ctrl.wrQLenPdf::35 0
|
||||
system.mem_ctrl.wrQLenPdf::36 0
|
||||
system.mem_ctrl.wrQLenPdf::37 0
|
||||
system.mem_ctrl.wrQLenPdf::38 0
|
||||
system.mem_ctrl.wrQLenPdf::39 0
|
||||
system.mem_ctrl.wrQLenPdf::40 0
|
||||
system.mem_ctrl.wrQLenPdf::41 0
|
||||
system.mem_ctrl.wrQLenPdf::42 0
|
||||
system.mem_ctrl.wrQLenPdf::43 0
|
||||
system.mem_ctrl.wrQLenPdf::44 0
|
||||
system.mem_ctrl.wrQLenPdf::45 0
|
||||
system.mem_ctrl.wrQLenPdf::46 0
|
||||
system.mem_ctrl.wrQLenPdf::47 0
|
||||
system.mem_ctrl.wrQLenPdf::48 0
|
||||
system.mem_ctrl.wrQLenPdf::49 0
|
||||
system.mem_ctrl.wrQLenPdf::50 0
|
||||
system.mem_ctrl.wrQLenPdf::51 0
|
||||
system.mem_ctrl.wrQLenPdf::52 0
|
||||
system.mem_ctrl.wrQLenPdf::53 0
|
||||
system.mem_ctrl.wrQLenPdf::54 0
|
||||
system.mem_ctrl.wrQLenPdf::55 0
|
||||
system.mem_ctrl.wrQLenPdf::56 0
|
||||
system.mem_ctrl.wrQLenPdf::57 0
|
||||
system.mem_ctrl.wrQLenPdf::58 0
|
||||
system.mem_ctrl.wrQLenPdf::59 0
|
||||
system.mem_ctrl.wrQLenPdf::60 0
|
||||
system.mem_ctrl.wrQLenPdf::61 0
|
||||
system.mem_ctrl.wrQLenPdf::62 0
|
||||
system.mem_ctrl.wrQLenPdf::63 0
|
||||
system.mem_ctrl.bytesPerActivate::samples 856
|
||||
system.mem_ctrl.bytesPerActivate::mean 618.018692
|
||||
system.mem_ctrl.bytesPerActivate::gmean 421.107711
|
||||
system.mem_ctrl.bytesPerActivate::stdev 393.969749
|
||||
system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29%
|
||||
system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05%
|
||||
system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58%
|
||||
system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65%
|
||||
system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31%
|
||||
system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04%
|
||||
system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24%
|
||||
system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00%
|
||||
system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00%
|
||||
system.mem_ctrl.bytesPerActivate::total 856
|
||||
system.mem_ctrl.rdPerTurnAround::samples 7
|
||||
system.mem_ctrl.rdPerTurnAround::mean 1165.285714
|
||||
system.mem_ctrl.rdPerTurnAround::gmean 941.793638
|
||||
system.mem_ctrl.rdPerTurnAround::stdev 714.559471
|
||||
system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29%
|
||||
system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57%
|
||||
system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86%
|
||||
system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14%
|
||||
system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43%
|
||||
system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71%
|
||||
system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00%
|
||||
system.mem_ctrl.rdPerTurnAround::total 7
|
||||
system.mem_ctrl.wrPerTurnAround::samples 7
|
||||
system.mem_ctrl.wrPerTurnAround::mean 16
|
||||
system.mem_ctrl.wrPerTurnAround::gmean 16.000000
|
||||
system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00%
|
||||
system.mem_ctrl.wrPerTurnAround::total 7
|
||||
system.mem_ctrl.totQLat 82521500
|
||||
system.mem_ctrl.totMemAccLat 236402750
|
||||
system.mem_ctrl.totBusLat 41035000
|
||||
system.mem_ctrl.avgQLat 10055.01
|
||||
system.mem_ctrl.avgBusLat 5000.00
|
||||
system.mem_ctrl.avgMemAccLat 28805.01
|
||||
system.mem_ctrl.avgRdBW 1034.28
|
||||
system.mem_ctrl.avgWrBW 14.11
|
||||
system.mem_ctrl.avgRdBWSys 128.86
|
||||
system.mem_ctrl.avgWrBWSys 14.10
|
||||
system.mem_ctrl.peakBW 12800.00
|
||||
system.mem_ctrl.busUtil 8.19
|
||||
system.mem_ctrl.busUtilRead 8.08
|
||||
system.mem_ctrl.busUtilWrite 0.11
|
||||
system.mem_ctrl.avgRdQLen 1.00
|
||||
system.mem_ctrl.avgWrQLen 23.79
|
||||
system.mem_ctrl.readRowHits 7358
|
||||
system.mem_ctrl.writeRowHits 98
|
||||
system.mem_ctrl.readRowHitRate 89.66
|
||||
system.mem_ctrl.writeRowHitRate 74.81
|
||||
system.mem_ctrl.avgGap 54545.49
|
||||
system.mem_ctrl.pageHitRate 89.42
|
||||
system.mem_ctrl_0.actEnergy 3127320
|
||||
system.mem_ctrl_0.preEnergy 1647030
|
||||
system.mem_ctrl_0.readEnergy 37149420
|
||||
system.mem_ctrl_0.writeEnergy 52200
|
||||
system.mem_ctrl_0.refreshEnergy 36263760.000000
|
||||
system.mem_ctrl_0.actBackEnergy 70559160
|
||||
system.mem_ctrl_0.preBackEnergy 1716480
|
||||
system.mem_ctrl_0.actPowerDownEnergy 113314290
|
||||
system.mem_ctrl_0.prePowerDownEnergy 13222080
|
||||
system.mem_ctrl_0.selfRefreshEnergy 17426520
|
||||
system.mem_ctrl_0.totalEnergy 294478260
|
||||
system.mem_ctrl_0.averagePower 579.862821
|
||||
system.mem_ctrl_0.totalIdleTime 347720500
|
||||
system.mem_ctrl_0.memoryStateTime::IDLE 1584000
|
||||
system.mem_ctrl_0.memoryStateTime::REF 15358000
|
||||
system.mem_ctrl_0.memoryStateTime::SREF 65707000
|
||||
system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500
|
||||
system.mem_ctrl_0.memoryStateTime::ACT 142245250
|
||||
system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250
|
||||
system.mem_ctrl_1.actEnergy 3034500
|
||||
system.mem_ctrl_1.preEnergy 1601490
|
||||
system.mem_ctrl_1.readEnergy 21441420
|
||||
system.mem_ctrl_1.writeEnergy 532440
|
||||
system.mem_ctrl_1.refreshEnergy 39336960.000000
|
||||
system.mem_ctrl_1.actBackEnergy 51598110
|
||||
system.mem_ctrl_1.preBackEnergy 1155360
|
||||
system.mem_ctrl_1.actPowerDownEnergy 151289970
|
||||
system.mem_ctrl_1.prePowerDownEnergy 18740160
|
||||
system.mem_ctrl_1.selfRefreshEnergy 3216240
|
||||
system.mem_ctrl_1.totalEnergy 291946650
|
||||
system.mem_ctrl_1.averagePower 574.877779
|
||||
system.mem_ctrl_1.totalIdleTime 391725750
|
||||
system.mem_ctrl_1.memoryStateTime::IDLE 757000
|
||||
system.mem_ctrl_1.memoryStateTime::REF 16646000
|
||||
system.mem_ctrl_1.memoryStateTime::SREF 11100000
|
||||
system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500
|
||||
system.mem_ctrl_1.memoryStateTime::ACT 98712250
|
||||
system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250
|
||||
system.pwrStateResidencyTicks::UNDEFINED 507841000
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000
|
||||
system.cpu.apic_clk_domain.clock 16000
|
||||
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000
|
||||
system.cpu.workload.numSyscalls 11
|
||||
system.cpu.pwrStateResidencyTicks::ON 507841000
|
||||
system.cpu.numCycles 507841
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 5712
|
||||
system.cpu.committedOps 10314
|
||||
system.cpu.num_int_alu_accesses 10205
|
||||
system.cpu.num_fp_alu_accesses 0
|
||||
system.cpu.num_func_calls 221
|
||||
system.cpu.num_conditional_control_insts 986
|
||||
system.cpu.num_int_insts 10205
|
||||
system.cpu.num_fp_insts 0
|
||||
system.cpu.num_int_register_reads 19296
|
||||
system.cpu.num_int_register_writes 7977
|
||||
system.cpu.num_fp_register_reads 0
|
||||
system.cpu.num_fp_register_writes 0
|
||||
system.cpu.num_cc_register_reads 7020
|
||||
system.cpu.num_cc_register_writes 3825
|
||||
system.cpu.num_mem_refs 2025
|
||||
system.cpu.num_load_insts 1084
|
||||
system.cpu.num_store_insts 941
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 507841
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 1306
|
||||
system.cpu.op_class::No_OpClass 1 0.01% 0.01%
|
||||
system.cpu.op_class::IntAlu 8275 80.23% 80.24%
|
||||
system.cpu.op_class::IntMult 6 0.06% 80.30%
|
||||
system.cpu.op_class::IntDiv 7 0.07% 80.37%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37%
|
||||
system.cpu.op_class::MemRead 1084 10.51% 90.88%
|
||||
system.cpu.op_class::MemWrite 941 9.12% 100.00%
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
|
||||
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 10314
|
||||
system.membus.snoop_filter.tot_requests 0
|
||||
system.membus.snoop_filter.hit_single_requests 0
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 507841000
|
||||
system.membus.trans_dist::ReadReq 8368
|
||||
system.membus.trans_dist::ReadResp 8367
|
||||
system.membus.trans_dist::WriteReq 941
|
||||
system.membus.trans_dist::WriteResp 941
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14567
|
||||
system.membus.pkt_count_system.cpu.icache_port::total 14567
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050
|
||||
system.membus.pkt_count_system.cpu.dcache_port::total 4050
|
||||
system.membus.pkt_count::total 18617
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264
|
||||
system.membus.pkt_size_system.cpu.icache_port::total 58264
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327
|
||||
system.membus.pkt_size_system.cpu.dcache_port::total 14327
|
||||
system.membus.pkt_size::total 72591
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 9309
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 9309 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 9309
|
||||
system.membus.reqLayer2.occupancy 10250000
|
||||
system.membus.reqLayer2.utilization 2.0
|
||||
system.membus.respLayer0.occupancy 16544750
|
||||
system.membus.respLayer0.utilization 3.3
|
||||
system.membus.respLayer1.occupancy 3432250
|
||||
system.membus.respLayer1.utilization 0.7
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,487 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kvm_vm=Null
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.mem_ctrl
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[2]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
children=voltage_domain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.clk_domain.voltage_domain
|
||||
|
||||
[system.clk_domain.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=apic_clk_domain dcache dtb icache interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=-1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=65536
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.l2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=65536
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=16384
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.l2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=16384
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
int_master=system.membus.slave[1]
|
||||
int_slave=system.membus.master[1]
|
||||
pio=system.membus.master[0]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=tests/test-progs/hello/bin/x86/linux/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.l2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.l2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.l2cache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.l2bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
|
||||
[system.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=262144
|
||||
tag_latency=20
|
||||
|
||||
[system.mem_ctrl]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:536870911:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port
|
||||
slave=system.l2cache.mem_side system.cpu.interrupts.int_master system.system_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
@@ -1,14 +0,0 @@
|
||||
Redirecting stdout to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level/simout
|
||||
Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 19:05:53
|
||||
gem5 started Apr 3 2017 19:06:21
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87157
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Beginning simulation!
|
||||
Hello world!
|
||||
Exiting @ tick 58513000 because exiting with last active thread context
|
||||
@@ -1,722 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000059
|
||||
sim_ticks 58513000
|
||||
final_tick 58513000
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 157408
|
||||
host_op_rate 284057
|
||||
host_tick_rate 1610644917
|
||||
host_mem_usage 667152
|
||||
host_seconds 0.04
|
||||
sim_insts 5712
|
||||
sim_ops 10314
|
||||
system.clk_domain.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.mem_ctrl.bytes_read::cpu.inst 14656
|
||||
system.mem_ctrl.bytes_read::cpu.data 8640
|
||||
system.mem_ctrl.bytes_read::total 23296
|
||||
system.mem_ctrl.bytes_inst_read::cpu.inst 14656
|
||||
system.mem_ctrl.bytes_inst_read::total 14656
|
||||
system.mem_ctrl.num_reads::cpu.inst 229
|
||||
system.mem_ctrl.num_reads::cpu.data 135
|
||||
system.mem_ctrl.num_reads::total 364
|
||||
system.mem_ctrl.bw_read::cpu.inst 250474254
|
||||
system.mem_ctrl.bw_read::cpu.data 147659494
|
||||
system.mem_ctrl.bw_read::total 398133748
|
||||
system.mem_ctrl.bw_inst_read::cpu.inst 250474254
|
||||
system.mem_ctrl.bw_inst_read::total 250474254
|
||||
system.mem_ctrl.bw_total::cpu.inst 250474254
|
||||
system.mem_ctrl.bw_total::cpu.data 147659494
|
||||
system.mem_ctrl.bw_total::total 398133748
|
||||
system.mem_ctrl.readReqs 364
|
||||
system.mem_ctrl.writeReqs 0
|
||||
system.mem_ctrl.readBursts 364
|
||||
system.mem_ctrl.writeBursts 0
|
||||
system.mem_ctrl.bytesReadDRAM 23296
|
||||
system.mem_ctrl.bytesReadWrQ 0
|
||||
system.mem_ctrl.bytesWritten 0
|
||||
system.mem_ctrl.bytesReadSys 23296
|
||||
system.mem_ctrl.bytesWrittenSys 0
|
||||
system.mem_ctrl.servicedByWrQ 0
|
||||
system.mem_ctrl.mergedWrBursts 0
|
||||
system.mem_ctrl.neitherReadNorWriteReqs 0
|
||||
system.mem_ctrl.perBankRdBursts::0 30
|
||||
system.mem_ctrl.perBankRdBursts::1 1
|
||||
system.mem_ctrl.perBankRdBursts::2 5
|
||||
system.mem_ctrl.perBankRdBursts::3 8
|
||||
system.mem_ctrl.perBankRdBursts::4 43
|
||||
system.mem_ctrl.perBankRdBursts::5 40
|
||||
system.mem_ctrl.perBankRdBursts::6 13
|
||||
system.mem_ctrl.perBankRdBursts::7 24
|
||||
system.mem_ctrl.perBankRdBursts::8 17
|
||||
system.mem_ctrl.perBankRdBursts::9 71
|
||||
system.mem_ctrl.perBankRdBursts::10 62
|
||||
system.mem_ctrl.perBankRdBursts::11 14
|
||||
system.mem_ctrl.perBankRdBursts::12 2
|
||||
system.mem_ctrl.perBankRdBursts::13 14
|
||||
system.mem_ctrl.perBankRdBursts::14 4
|
||||
system.mem_ctrl.perBankRdBursts::15 16
|
||||
system.mem_ctrl.perBankWrBursts::0 0
|
||||
system.mem_ctrl.perBankWrBursts::1 0
|
||||
system.mem_ctrl.perBankWrBursts::2 0
|
||||
system.mem_ctrl.perBankWrBursts::3 0
|
||||
system.mem_ctrl.perBankWrBursts::4 0
|
||||
system.mem_ctrl.perBankWrBursts::5 0
|
||||
system.mem_ctrl.perBankWrBursts::6 0
|
||||
system.mem_ctrl.perBankWrBursts::7 0
|
||||
system.mem_ctrl.perBankWrBursts::8 0
|
||||
system.mem_ctrl.perBankWrBursts::9 0
|
||||
system.mem_ctrl.perBankWrBursts::10 0
|
||||
system.mem_ctrl.perBankWrBursts::11 0
|
||||
system.mem_ctrl.perBankWrBursts::12 0
|
||||
system.mem_ctrl.perBankWrBursts::13 0
|
||||
system.mem_ctrl.perBankWrBursts::14 0
|
||||
system.mem_ctrl.perBankWrBursts::15 0
|
||||
system.mem_ctrl.numRdRetry 0
|
||||
system.mem_ctrl.numWrRetry 0
|
||||
system.mem_ctrl.totGap 58376000
|
||||
system.mem_ctrl.readPktSize::0 0
|
||||
system.mem_ctrl.readPktSize::1 0
|
||||
system.mem_ctrl.readPktSize::2 0
|
||||
system.mem_ctrl.readPktSize::3 0
|
||||
system.mem_ctrl.readPktSize::4 0
|
||||
system.mem_ctrl.readPktSize::5 0
|
||||
system.mem_ctrl.readPktSize::6 364
|
||||
system.mem_ctrl.writePktSize::0 0
|
||||
system.mem_ctrl.writePktSize::1 0
|
||||
system.mem_ctrl.writePktSize::2 0
|
||||
system.mem_ctrl.writePktSize::3 0
|
||||
system.mem_ctrl.writePktSize::4 0
|
||||
system.mem_ctrl.writePktSize::5 0
|
||||
system.mem_ctrl.writePktSize::6 0
|
||||
system.mem_ctrl.rdQLenPdf::0 364
|
||||
system.mem_ctrl.rdQLenPdf::1 0
|
||||
system.mem_ctrl.rdQLenPdf::2 0
|
||||
system.mem_ctrl.rdQLenPdf::3 0
|
||||
system.mem_ctrl.rdQLenPdf::4 0
|
||||
system.mem_ctrl.rdQLenPdf::5 0
|
||||
system.mem_ctrl.rdQLenPdf::6 0
|
||||
system.mem_ctrl.rdQLenPdf::7 0
|
||||
system.mem_ctrl.rdQLenPdf::8 0
|
||||
system.mem_ctrl.rdQLenPdf::9 0
|
||||
system.mem_ctrl.rdQLenPdf::10 0
|
||||
system.mem_ctrl.rdQLenPdf::11 0
|
||||
system.mem_ctrl.rdQLenPdf::12 0
|
||||
system.mem_ctrl.rdQLenPdf::13 0
|
||||
system.mem_ctrl.rdQLenPdf::14 0
|
||||
system.mem_ctrl.rdQLenPdf::15 0
|
||||
system.mem_ctrl.rdQLenPdf::16 0
|
||||
system.mem_ctrl.rdQLenPdf::17 0
|
||||
system.mem_ctrl.rdQLenPdf::18 0
|
||||
system.mem_ctrl.rdQLenPdf::19 0
|
||||
system.mem_ctrl.rdQLenPdf::20 0
|
||||
system.mem_ctrl.rdQLenPdf::21 0
|
||||
system.mem_ctrl.rdQLenPdf::22 0
|
||||
system.mem_ctrl.rdQLenPdf::23 0
|
||||
system.mem_ctrl.rdQLenPdf::24 0
|
||||
system.mem_ctrl.rdQLenPdf::25 0
|
||||
system.mem_ctrl.rdQLenPdf::26 0
|
||||
system.mem_ctrl.rdQLenPdf::27 0
|
||||
system.mem_ctrl.rdQLenPdf::28 0
|
||||
system.mem_ctrl.rdQLenPdf::29 0
|
||||
system.mem_ctrl.rdQLenPdf::30 0
|
||||
system.mem_ctrl.rdQLenPdf::31 0
|
||||
system.mem_ctrl.wrQLenPdf::0 0
|
||||
system.mem_ctrl.wrQLenPdf::1 0
|
||||
system.mem_ctrl.wrQLenPdf::2 0
|
||||
system.mem_ctrl.wrQLenPdf::3 0
|
||||
system.mem_ctrl.wrQLenPdf::4 0
|
||||
system.mem_ctrl.wrQLenPdf::5 0
|
||||
system.mem_ctrl.wrQLenPdf::6 0
|
||||
system.mem_ctrl.wrQLenPdf::7 0
|
||||
system.mem_ctrl.wrQLenPdf::8 0
|
||||
system.mem_ctrl.wrQLenPdf::9 0
|
||||
system.mem_ctrl.wrQLenPdf::10 0
|
||||
system.mem_ctrl.wrQLenPdf::11 0
|
||||
system.mem_ctrl.wrQLenPdf::12 0
|
||||
system.mem_ctrl.wrQLenPdf::13 0
|
||||
system.mem_ctrl.wrQLenPdf::14 0
|
||||
system.mem_ctrl.wrQLenPdf::15 0
|
||||
system.mem_ctrl.wrQLenPdf::16 0
|
||||
system.mem_ctrl.wrQLenPdf::17 0
|
||||
system.mem_ctrl.wrQLenPdf::18 0
|
||||
system.mem_ctrl.wrQLenPdf::19 0
|
||||
system.mem_ctrl.wrQLenPdf::20 0
|
||||
system.mem_ctrl.wrQLenPdf::21 0
|
||||
system.mem_ctrl.wrQLenPdf::22 0
|
||||
system.mem_ctrl.wrQLenPdf::23 0
|
||||
system.mem_ctrl.wrQLenPdf::24 0
|
||||
system.mem_ctrl.wrQLenPdf::25 0
|
||||
system.mem_ctrl.wrQLenPdf::26 0
|
||||
system.mem_ctrl.wrQLenPdf::27 0
|
||||
system.mem_ctrl.wrQLenPdf::28 0
|
||||
system.mem_ctrl.wrQLenPdf::29 0
|
||||
system.mem_ctrl.wrQLenPdf::30 0
|
||||
system.mem_ctrl.wrQLenPdf::31 0
|
||||
system.mem_ctrl.wrQLenPdf::32 0
|
||||
system.mem_ctrl.wrQLenPdf::33 0
|
||||
system.mem_ctrl.wrQLenPdf::34 0
|
||||
system.mem_ctrl.wrQLenPdf::35 0
|
||||
system.mem_ctrl.wrQLenPdf::36 0
|
||||
system.mem_ctrl.wrQLenPdf::37 0
|
||||
system.mem_ctrl.wrQLenPdf::38 0
|
||||
system.mem_ctrl.wrQLenPdf::39 0
|
||||
system.mem_ctrl.wrQLenPdf::40 0
|
||||
system.mem_ctrl.wrQLenPdf::41 0
|
||||
system.mem_ctrl.wrQLenPdf::42 0
|
||||
system.mem_ctrl.wrQLenPdf::43 0
|
||||
system.mem_ctrl.wrQLenPdf::44 0
|
||||
system.mem_ctrl.wrQLenPdf::45 0
|
||||
system.mem_ctrl.wrQLenPdf::46 0
|
||||
system.mem_ctrl.wrQLenPdf::47 0
|
||||
system.mem_ctrl.wrQLenPdf::48 0
|
||||
system.mem_ctrl.wrQLenPdf::49 0
|
||||
system.mem_ctrl.wrQLenPdf::50 0
|
||||
system.mem_ctrl.wrQLenPdf::51 0
|
||||
system.mem_ctrl.wrQLenPdf::52 0
|
||||
system.mem_ctrl.wrQLenPdf::53 0
|
||||
system.mem_ctrl.wrQLenPdf::54 0
|
||||
system.mem_ctrl.wrQLenPdf::55 0
|
||||
system.mem_ctrl.wrQLenPdf::56 0
|
||||
system.mem_ctrl.wrQLenPdf::57 0
|
||||
system.mem_ctrl.wrQLenPdf::58 0
|
||||
system.mem_ctrl.wrQLenPdf::59 0
|
||||
system.mem_ctrl.wrQLenPdf::60 0
|
||||
system.mem_ctrl.wrQLenPdf::61 0
|
||||
system.mem_ctrl.wrQLenPdf::62 0
|
||||
system.mem_ctrl.wrQLenPdf::63 0
|
||||
system.mem_ctrl.bytesPerActivate::samples 108
|
||||
system.mem_ctrl.bytesPerActivate::mean 199.703704
|
||||
system.mem_ctrl.bytesPerActivate::gmean 135.091179
|
||||
system.mem_ctrl.bytesPerActivate::stdev 199.282229
|
||||
system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15%
|
||||
system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59%
|
||||
system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48%
|
||||
system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89%
|
||||
system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37%
|
||||
system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22%
|
||||
system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15%
|
||||
system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07%
|
||||
system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00%
|
||||
system.mem_ctrl.bytesPerActivate::total 108
|
||||
system.mem_ctrl.totQLat 5858750
|
||||
system.mem_ctrl.totMemAccLat 12683750
|
||||
system.mem_ctrl.totBusLat 1820000
|
||||
system.mem_ctrl.avgQLat 16095.47
|
||||
system.mem_ctrl.avgBusLat 5000.00
|
||||
system.mem_ctrl.avgMemAccLat 34845.47
|
||||
system.mem_ctrl.avgRdBW 398.13
|
||||
system.mem_ctrl.avgWrBW 0.00
|
||||
system.mem_ctrl.avgRdBWSys 398.13
|
||||
system.mem_ctrl.avgWrBWSys 0.00
|
||||
system.mem_ctrl.peakBW 12800.00
|
||||
system.mem_ctrl.busUtil 3.11
|
||||
system.mem_ctrl.busUtilRead 3.11
|
||||
system.mem_ctrl.busUtilWrite 0.00
|
||||
system.mem_ctrl.avgRdQLen 1.00
|
||||
system.mem_ctrl.avgWrQLen 0.00
|
||||
system.mem_ctrl.readRowHits 248
|
||||
system.mem_ctrl.writeRowHits 0
|
||||
system.mem_ctrl.readRowHitRate 68.13
|
||||
system.mem_ctrl.writeRowHitRate nan
|
||||
system.mem_ctrl.avgGap 160373.63
|
||||
system.mem_ctrl.pageHitRate 68.13
|
||||
system.mem_ctrl_0.actEnergy 292740
|
||||
system.mem_ctrl_0.preEnergy 136620
|
||||
system.mem_ctrl_0.readEnergy 1170960
|
||||
system.mem_ctrl_0.writeEnergy 0
|
||||
system.mem_ctrl_0.refreshEnergy 4302480.000000
|
||||
system.mem_ctrl_0.actBackEnergy 2975970
|
||||
system.mem_ctrl_0.preBackEnergy 96960
|
||||
system.mem_ctrl_0.actPowerDownEnergy 20164320
|
||||
system.mem_ctrl_0.prePowerDownEnergy 2885760
|
||||
system.mem_ctrl_0.selfRefreshEnergy 0
|
||||
system.mem_ctrl_0.totalEnergy 32025810
|
||||
system.mem_ctrl_0.averagePower 547.321100
|
||||
system.mem_ctrl_0.totalIdleTime 51467750
|
||||
system.mem_ctrl_0.memoryStateTime::IDLE 59000
|
||||
system.mem_ctrl_0.memoryStateTime::REF 1820000
|
||||
system.mem_ctrl_0.memoryStateTime::SREF 0
|
||||
system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000
|
||||
system.mem_ctrl_0.memoryStateTime::ACT 4902000
|
||||
system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000
|
||||
system.mem_ctrl_1.actEnergy 535500
|
||||
system.mem_ctrl_1.preEnergy 273240
|
||||
system.mem_ctrl_1.readEnergy 1428000
|
||||
system.mem_ctrl_1.writeEnergy 0
|
||||
system.mem_ctrl_1.refreshEnergy 4302480.000000
|
||||
system.mem_ctrl_1.actBackEnergy 3735210
|
||||
system.mem_ctrl_1.preBackEnergy 150720
|
||||
system.mem_ctrl_1.actPowerDownEnergy 22328040
|
||||
system.mem_ctrl_1.prePowerDownEnergy 370560
|
||||
system.mem_ctrl_1.selfRefreshEnergy 0
|
||||
system.mem_ctrl_1.totalEnergy 33123750
|
||||
system.mem_ctrl_1.averagePower 566.084895
|
||||
system.mem_ctrl_1.totalIdleTime 49870500
|
||||
system.mem_ctrl_1.memoryStateTime::IDLE 184000
|
||||
system.mem_ctrl_1.memoryStateTime::REF 1820000
|
||||
system.mem_ctrl_1.memoryStateTime::SREF 0
|
||||
system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000
|
||||
system.mem_ctrl_1.memoryStateTime::ACT 6563000
|
||||
system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000
|
||||
system.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.cpu.apic_clk_domain.clock 16000
|
||||
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.cpu.workload.numSyscalls 11
|
||||
system.cpu.pwrStateResidencyTicks::ON 58513000
|
||||
system.cpu.numCycles 58513
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 5712
|
||||
system.cpu.committedOps 10314
|
||||
system.cpu.num_int_alu_accesses 10205
|
||||
system.cpu.num_fp_alu_accesses 0
|
||||
system.cpu.num_func_calls 221
|
||||
system.cpu.num_conditional_control_insts 986
|
||||
system.cpu.num_int_insts 10205
|
||||
system.cpu.num_fp_insts 0
|
||||
system.cpu.num_int_register_reads 19296
|
||||
system.cpu.num_int_register_writes 7977
|
||||
system.cpu.num_fp_register_reads 0
|
||||
system.cpu.num_fp_register_writes 0
|
||||
system.cpu.num_cc_register_reads 7020
|
||||
system.cpu.num_cc_register_writes 3825
|
||||
system.cpu.num_mem_refs 2025
|
||||
system.cpu.num_load_insts 1084
|
||||
system.cpu.num_store_insts 941
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 58513
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 1306
|
||||
system.cpu.op_class::No_OpClass 1 0.01% 0.01%
|
||||
system.cpu.op_class::IntAlu 8275 80.23% 80.24%
|
||||
system.cpu.op_class::IntMult 6 0.06% 80.30%
|
||||
system.cpu.op_class::IntDiv 7 0.07% 80.37%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 80.37%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37%
|
||||
system.cpu.op_class::MemRead 1084 10.51% 90.88%
|
||||
system.cpu.op_class::MemWrite 941 9.12% 100.00%
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
|
||||
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 10314
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.cpu.dcache.tags.replacements 0
|
||||
system.cpu.dcache.tags.tagsinuse 81.299644
|
||||
system.cpu.dcache.tags.total_refs 1890
|
||||
system.cpu.dcache.tags.sampled_refs 135
|
||||
system.cpu.dcache.tags.avg_refs 14
|
||||
system.cpu.dcache.tags.warmup_cycle 0
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.079394
|
||||
system.cpu.dcache.tags.occ_percent::total 0.079394
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 135
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 12
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 123
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836
|
||||
system.cpu.dcache.tags.tag_accesses 4185
|
||||
system.cpu.dcache.tags.data_accesses 4185
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1028
|
||||
system.cpu.dcache.ReadReq_hits::total 1028
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 862
|
||||
system.cpu.dcache.WriteReq_hits::total 862
|
||||
system.cpu.dcache.demand_hits::cpu.data 1890
|
||||
system.cpu.dcache.demand_hits::total 1890
|
||||
system.cpu.dcache.overall_hits::cpu.data 1890
|
||||
system.cpu.dcache.overall_hits::total 1890
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 56
|
||||
system.cpu.dcache.ReadReq_misses::total 56
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 79
|
||||
system.cpu.dcache.WriteReq_misses::total 79
|
||||
system.cpu.dcache.demand_misses::cpu.data 135
|
||||
system.cpu.dcache.demand_misses::total 135
|
||||
system.cpu.dcache.overall_misses::cpu.data 135
|
||||
system.cpu.dcache.overall_misses::total 135
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6406000
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8602000
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 15008000
|
||||
system.cpu.dcache.demand_miss_latency::total 15008000
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 15008000
|
||||
system.cpu.dcache.overall_miss_latency::total 15008000
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1084
|
||||
system.cpu.dcache.ReadReq_accesses::total 1084
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 941
|
||||
system.cpu.dcache.WriteReq_accesses::total 941
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2025
|
||||
system.cpu.dcache.demand_accesses::total 2025
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2025
|
||||
system.cpu.dcache.overall_accesses::total 2025
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.051661
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.051661
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083953
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.083953
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.066667
|
||||
system.cpu.dcache.demand_miss_rate::total 0.066667
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.066667
|
||||
system.cpu.dcache.overall_miss_rate::total 0.066667
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 111170.370370
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 111170.370370
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0
|
||||
system.cpu.dcache.blocked::no_mshrs 0
|
||||
system.cpu.dcache.blocked::no_targets 0
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 56
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 79
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 135
|
||||
system.cpu.dcache.demand_mshr_misses::total 135
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 135
|
||||
system.cpu.dcache.overall_mshr_misses::total 135
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14738000
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14738000
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083953
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.066667
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.066667
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.cpu.icache.tags.replacements 58
|
||||
system.cpu.icache.tags.tagsinuse 90.704136
|
||||
system.cpu.icache.tags.total_refs 7049
|
||||
system.cpu.icache.tags.sampled_refs 235
|
||||
system.cpu.icache.tags.avg_refs 29.995745
|
||||
system.cpu.icache.tags.warmup_cycle 0
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354313
|
||||
system.cpu.icache.tags.occ_percent::total 0.354313
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 177
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 43
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 134
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.691406
|
||||
system.cpu.icache.tags.tag_accesses 14803
|
||||
system.cpu.icache.tags.data_accesses 14803
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 7049
|
||||
system.cpu.icache.ReadReq_hits::total 7049
|
||||
system.cpu.icache.demand_hits::cpu.inst 7049
|
||||
system.cpu.icache.demand_hits::total 7049
|
||||
system.cpu.icache.overall_hits::cpu.inst 7049
|
||||
system.cpu.icache.overall_hits::total 7049
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 235
|
||||
system.cpu.icache.ReadReq_misses::total 235
|
||||
system.cpu.icache.demand_misses::cpu.inst 235
|
||||
system.cpu.icache.demand_misses::total 235
|
||||
system.cpu.icache.overall_misses::cpu.inst 235
|
||||
system.cpu.icache.overall_misses::total 235
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25629000
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25629000
|
||||
system.cpu.icache.demand_miss_latency::total 25629000
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25629000
|
||||
system.cpu.icache.overall_miss_latency::total 25629000
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 7284
|
||||
system.cpu.icache.ReadReq_accesses::total 7284
|
||||
system.cpu.icache.demand_accesses::cpu.inst 7284
|
||||
system.cpu.icache.demand_accesses::total 7284
|
||||
system.cpu.icache.overall_accesses::cpu.inst 7284
|
||||
system.cpu.icache.overall_accesses::total 7284
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032262
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.032262
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.032262
|
||||
system.cpu.icache.demand_miss_rate::total 0.032262
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.032262
|
||||
system.cpu.icache.overall_miss_rate::total 0.032262
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468
|
||||
system.cpu.icache.demand_avg_miss_latency::total 109059.574468
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468
|
||||
system.cpu.icache.overall_avg_miss_latency::total 109059.574468
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.icache.blocked_cycles::no_targets 0
|
||||
system.cpu.icache.blocked::no_mshrs 0
|
||||
system.cpu.icache.blocked::no_targets 0
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 235
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 235
|
||||
system.cpu.icache.demand_mshr_misses::total 235
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 235
|
||||
system.cpu.icache.overall_mshr_misses::total 235
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 25159000
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 25159000
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032262
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032262
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032262
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.032262
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032262
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.032262
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468
|
||||
system.l2bus.snoop_filter.tot_requests 428
|
||||
system.l2bus.snoop_filter.hit_single_requests 59
|
||||
system.l2bus.snoop_filter.hit_multi_requests 0
|
||||
system.l2bus.snoop_filter.tot_snoops 0
|
||||
system.l2bus.snoop_filter.hit_single_snoops 0
|
||||
system.l2bus.snoop_filter.hit_multi_snoops 0
|
||||
system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.l2bus.trans_dist::ReadResp 291
|
||||
system.l2bus.trans_dist::CleanEvict 58
|
||||
system.l2bus.trans_dist::ReadExReq 79
|
||||
system.l2bus.trans_dist::ReadExResp 79
|
||||
system.l2bus.trans_dist::ReadSharedReq 291
|
||||
system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528
|
||||
system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270
|
||||
system.l2bus.pkt_count::total 798
|
||||
system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15040
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640
|
||||
system.l2bus.pkt_size::total 23680
|
||||
system.l2bus.snoops 0
|
||||
system.l2bus.snoopTraffic 0
|
||||
system.l2bus.snoop_fanout::samples 370
|
||||
system.l2bus.snoop_fanout::mean 0.002703
|
||||
system.l2bus.snoop_fanout::stdev 0.051988
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.l2bus.snoop_fanout::0 369 99.73% 99.73%
|
||||
system.l2bus.snoop_fanout::1 1 0.27% 100.00%
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00%
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.l2bus.snoop_fanout::min_value 0
|
||||
system.l2bus.snoop_fanout::max_value 1
|
||||
system.l2bus.snoop_fanout::total 370
|
||||
system.l2bus.reqLayer0.occupancy 428000
|
||||
system.l2bus.reqLayer0.utilization 0.7
|
||||
system.l2bus.respLayer0.occupancy 705000
|
||||
system.l2bus.respLayer0.utilization 1.2
|
||||
system.l2bus.respLayer1.occupancy 405000
|
||||
system.l2bus.respLayer1.utilization 0.7
|
||||
system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.l2cache.tags.replacements 0
|
||||
system.l2cache.tags.tagsinuse 187.541609
|
||||
system.l2cache.tags.total_refs 64
|
||||
system.l2cache.tags.sampled_refs 364
|
||||
system.l2cache.tags.avg_refs 0.175824
|
||||
system.l2cache.tags.warmup_cycle 0
|
||||
system.l2cache.tags.occ_blocks::cpu.inst 106.193515
|
||||
system.l2cache.tags.occ_blocks::cpu.data 81.348095
|
||||
system.l2cache.tags.occ_percent::cpu.inst 0.025926
|
||||
system.l2cache.tags.occ_percent::cpu.data 0.019860
|
||||
system.l2cache.tags.occ_percent::total 0.045787
|
||||
system.l2cache.tags.occ_task_id_blocks::1024 364
|
||||
system.l2cache.tags.age_task_id_blocks_1024::0 55
|
||||
system.l2cache.tags.age_task_id_blocks_1024::1 309
|
||||
system.l2cache.tags.occ_task_id_percent::1024 0.088867
|
||||
system.l2cache.tags.tag_accesses 3788
|
||||
system.l2cache.tags.data_accesses 3788
|
||||
system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.l2cache.ReadSharedReq_hits::cpu.inst 6
|
||||
system.l2cache.ReadSharedReq_hits::total 6
|
||||
system.l2cache.demand_hits::cpu.inst 6
|
||||
system.l2cache.demand_hits::total 6
|
||||
system.l2cache.overall_hits::cpu.inst 6
|
||||
system.l2cache.overall_hits::total 6
|
||||
system.l2cache.ReadExReq_misses::cpu.data 79
|
||||
system.l2cache.ReadExReq_misses::total 79
|
||||
system.l2cache.ReadSharedReq_misses::cpu.inst 229
|
||||
system.l2cache.ReadSharedReq_misses::cpu.data 56
|
||||
system.l2cache.ReadSharedReq_misses::total 285
|
||||
system.l2cache.demand_misses::cpu.inst 229
|
||||
system.l2cache.demand_misses::cpu.data 135
|
||||
system.l2cache.demand_misses::total 364
|
||||
system.l2cache.overall_misses::cpu.inst 229
|
||||
system.l2cache.overall_misses::cpu.data 135
|
||||
system.l2cache.overall_misses::total 364
|
||||
system.l2cache.ReadExReq_miss_latency::cpu.data 8207000
|
||||
system.l2cache.ReadExReq_miss_latency::total 8207000
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000
|
||||
system.l2cache.ReadSharedReq_miss_latency::total 30452000
|
||||
system.l2cache.demand_miss_latency::cpu.inst 24326000
|
||||
system.l2cache.demand_miss_latency::cpu.data 14333000
|
||||
system.l2cache.demand_miss_latency::total 38659000
|
||||
system.l2cache.overall_miss_latency::cpu.inst 24326000
|
||||
system.l2cache.overall_miss_latency::cpu.data 14333000
|
||||
system.l2cache.overall_miss_latency::total 38659000
|
||||
system.l2cache.ReadExReq_accesses::cpu.data 79
|
||||
system.l2cache.ReadExReq_accesses::total 79
|
||||
system.l2cache.ReadSharedReq_accesses::cpu.inst 235
|
||||
system.l2cache.ReadSharedReq_accesses::cpu.data 56
|
||||
system.l2cache.ReadSharedReq_accesses::total 291
|
||||
system.l2cache.demand_accesses::cpu.inst 235
|
||||
system.l2cache.demand_accesses::cpu.data 135
|
||||
system.l2cache.demand_accesses::total 370
|
||||
system.l2cache.overall_accesses::cpu.inst 235
|
||||
system.l2cache.overall_accesses::cpu.data 135
|
||||
system.l2cache.overall_accesses::total 370
|
||||
system.l2cache.ReadExReq_miss_rate::cpu.data 1
|
||||
system.l2cache.ReadExReq_miss_rate::total 1
|
||||
system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.974468
|
||||
system.l2cache.ReadSharedReq_miss_rate::cpu.data 1
|
||||
system.l2cache.ReadSharedReq_miss_rate::total 0.979381
|
||||
system.l2cache.demand_miss_rate::cpu.inst 0.974468
|
||||
system.l2cache.demand_miss_rate::cpu.data 1
|
||||
system.l2cache.demand_miss_rate::total 0.983784
|
||||
system.l2cache.overall_miss_rate::cpu.inst 0.974468
|
||||
system.l2cache.overall_miss_rate::cpu.data 1
|
||||
system.l2cache.overall_miss_rate::total 0.983784
|
||||
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949
|
||||
system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807
|
||||
system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236
|
||||
system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370
|
||||
system.l2cache.demand_avg_miss_latency::total 106206.043956
|
||||
system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236
|
||||
system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370
|
||||
system.l2cache.overall_avg_miss_latency::total 106206.043956
|
||||
system.l2cache.blocked_cycles::no_mshrs 0
|
||||
system.l2cache.blocked_cycles::no_targets 0
|
||||
system.l2cache.blocked::no_mshrs 0
|
||||
system.l2cache.blocked::no_targets 0
|
||||
system.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.l2cache.avg_blocked_cycles::no_targets nan
|
||||
system.l2cache.ReadExReq_mshr_misses::cpu.data 79
|
||||
system.l2cache.ReadExReq_mshr_misses::total 79
|
||||
system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229
|
||||
system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56
|
||||
system.l2cache.ReadSharedReq_mshr_misses::total 285
|
||||
system.l2cache.demand_mshr_misses::cpu.inst 229
|
||||
system.l2cache.demand_mshr_misses::cpu.data 135
|
||||
system.l2cache.demand_mshr_misses::total 364
|
||||
system.l2cache.overall_mshr_misses::cpu.inst 229
|
||||
system.l2cache.overall_mshr_misses::cpu.data 135
|
||||
system.l2cache.overall_mshr_misses::total 364
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::total 6627000
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.data 11633000
|
||||
system.l2cache.demand_mshr_miss_latency::total 31379000
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.data 11633000
|
||||
system.l2cache.overall_mshr_miss_latency::total 31379000
|
||||
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
|
||||
system.l2cache.ReadExReq_mshr_miss_rate::total 1
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381
|
||||
system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468
|
||||
system.l2cache.demand_mshr_miss_rate::cpu.data 1
|
||||
system.l2cache.demand_mshr_miss_rate::total 0.983784
|
||||
system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468
|
||||
system.l2cache.overall_mshr_miss_rate::cpu.data 1
|
||||
system.l2cache.overall_mshr_miss_rate::total 0.983784
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370
|
||||
system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370
|
||||
system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956
|
||||
system.membus.snoop_filter.tot_requests 364
|
||||
system.membus.snoop_filter.hit_single_requests 0
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 58513000
|
||||
system.membus.trans_dist::ReadResp 285
|
||||
system.membus.trans_dist::ReadExReq 79
|
||||
system.membus.trans_dist::ReadExResp 79
|
||||
system.membus.trans_dist::ReadSharedReq 285
|
||||
system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728
|
||||
system.membus.pkt_count_system.l2cache.mem_side::total 728
|
||||
system.membus.pkt_count::total 728
|
||||
system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296
|
||||
system.membus.pkt_size_system.l2cache.mem_side::total 23296
|
||||
system.membus.pkt_size::total 23296
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 364
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 364 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 364
|
||||
system.membus.reqLayer2.occupancy 364000
|
||||
system.membus.reqLayer2.utilization 0.6
|
||||
system.membus.respLayer0.occupancy 1951250
|
||||
system.membus.respLayer0.utilization 3.3
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,2 +0,0 @@
|
||||
|
||||
# Empty to satisfy run.py
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +0,0 @@
|
||||
warn: system.ruby.network adopting orphan SimObject param 'int_links'
|
||||
warn: system.ruby.network adopting orphan SimObject param 'ext_links'
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
|
||||
@@ -1,22 +0,0 @@
|
||||
Redirecting stdout to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO/simout
|
||||
Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 29 2017 16:09:06
|
||||
gem5 started Mar 29 2017 16:09:22
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54093
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO
|
||||
|
||||
Using GPU kernel code file(s) /usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23
|
||||
the gpu says:
|
||||
elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe
|
||||
Exiting @ tick 667407500 because exiting with last active thread context
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,5 +0,0 @@
|
||||
warn: system.ruby.network adopting orphan SimObject param 'int_links'
|
||||
warn: system.ruby.network adopting orphan SimObject param 'ext_links'
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
|
||||
@@ -1,21 +0,0 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 19 2016 13:36:44
|
||||
gem5 started Jan 19 2016 13:37:09
|
||||
gem5 executing on zizzer, pid 49676
|
||||
command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER
|
||||
|
||||
Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23
|
||||
the gpu says:
|
||||
elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe
|
||||
Exiting @ tick 314399500 because target called exit()
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,5 +0,0 @@
|
||||
warn: system.ruby.network adopting orphan SimObject param 'int_links'
|
||||
warn: system.ruby.network adopting orphan SimObject param 'ext_links'
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
|
||||
@@ -1,21 +0,0 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 19 2016 13:39:50
|
||||
gem5 started Jan 19 2016 13:40:22
|
||||
gem5 executing on zizzer, pid 50252
|
||||
command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Baseline -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Baseline
|
||||
|
||||
Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23
|
||||
the gpu says:
|
||||
elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe
|
||||
Exiting @ tick 548459500 because target called exit()
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -1,5 +0,0 @@
|
||||
warn: system.ruby.network adopting orphan SimObject param 'int_links'
|
||||
warn: system.ruby.network adopting orphan SimObject param 'ext_links'
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
|
||||
@@ -1,21 +0,0 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 19 2016 13:45:43
|
||||
gem5 started Jan 19 2016 13:46:17
|
||||
gem5 executing on zizzer, pid 51290
|
||||
command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Region -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Region
|
||||
|
||||
Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
Forcing maxCoalescedReqs to 32 (TLB assoc.)
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23
|
||||
the gpu says:
|
||||
elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe
|
||||
Exiting @ tick 468854500 because target called exit()
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,51 +0,0 @@
|
||||
#
|
||||
# Copyright (c) 2015 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# For use for simulation and test purposes only
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
# may be used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Author: Brad Beckmann
|
||||
#
|
||||
|
||||
from __future__ import print_function
|
||||
|
||||
executable = binpath('gpu-hello')
|
||||
kernel_path = os.path.dirname(executable)
|
||||
kernel_files = glob.glob(os.path.join(kernel_path, '*.asm'))
|
||||
if kernel_files:
|
||||
print("Using GPU kernel code file(s)", ",".join(kernel_files))
|
||||
else:
|
||||
fatal("Can't locate kernel code (.asm) in " + kernel_path)
|
||||
|
||||
driver = ClDriver(filename="hsa", codefile=kernel_files)
|
||||
root.system.cpu[2].cl_driver = driver
|
||||
root.system.cpu[0].workload = Process(cmd = 'gpu-hello',
|
||||
executable = binpath('gpu-hello'),
|
||||
drivers = [driver])
|
||||
|
||||
@@ -1,31 +0,0 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
m5.util.addToPath('../configs/common')
|
||||
from cpu2000 import eon_cook
|
||||
|
||||
workload = eon_cook(isa, opsys, 'mdred')
|
||||
root.system.cpu[0].workload = workload.makeProcess()
|
||||
@@ -1,28 +0,0 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
MemTest.max_loads=1e5
|
||||
MemTest.progress_interval=1e4
|
||||
@@ -1,330 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
@@ -1,12 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 17:55:48
|
||||
gem5 started Apr 3 2017 17:56:13
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54215
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-atomic
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 48960022500 because exiting with last active thread context
|
||||
@@ -1,258 +0,0 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@@ -1,262 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.048960
|
||||
sim_ticks 48960022500
|
||||
final_tick 48960022500
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 739512
|
||||
host_op_rate 945733
|
||||
host_tick_rate 510575162
|
||||
host_mem_usage 279300
|
||||
host_seconds 95.89
|
||||
sim_insts 70913204
|
||||
sim_ops 90688159
|
||||
system.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 48960022500
|
||||
system.physmem.bytes_read::cpu.inst 312580364
|
||||
system.physmem.bytes_read::cpu.data 106573345
|
||||
system.physmem.bytes_read::total 419153709
|
||||
system.physmem.bytes_inst_read::cpu.inst 312580364
|
||||
system.physmem.bytes_inst_read::total 312580364
|
||||
system.physmem.bytes_written::cpu.data 78660211
|
||||
system.physmem.bytes_written::total 78660211
|
||||
system.physmem.num_reads::cpu.inst 78145091
|
||||
system.physmem.num_reads::cpu.data 22919730
|
||||
system.physmem.num_reads::total 101064821
|
||||
system.physmem.num_writes::cpu.data 19865820
|
||||
system.physmem.num_writes::total 19865820
|
||||
system.physmem.bw_read::cpu.inst 6384399925
|
||||
system.physmem.bw_read::cpu.data 2176742157
|
||||
system.physmem.bw_read::total 8561142083
|
||||
system.physmem.bw_inst_read::cpu.inst 6384399925
|
||||
system.physmem.bw_inst_read::total 6384399925
|
||||
system.physmem.bw_write::cpu.data 1606621218
|
||||
system.physmem.bw_write::total 1606621218
|
||||
system.physmem.bw_total::cpu.inst 6384399925
|
||||
system.physmem.bw_total::cpu.data 3783363376
|
||||
system.physmem.bw_total::total 10167763301
|
||||
system.pwrStateResidencyTicks::UNDEFINED 48960022500
|
||||
system.cpu_clk_domain.clock 500
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500
|
||||
system.cpu.dtb.walker.walks 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dtb.inst_hits 0
|
||||
system.cpu.dtb.inst_misses 0
|
||||
system.cpu.dtb.read_hits 0
|
||||
system.cpu.dtb.read_misses 0
|
||||
system.cpu.dtb.write_hits 0
|
||||
system.cpu.dtb.write_misses 0
|
||||
system.cpu.dtb.flush_tlb 0
|
||||
system.cpu.dtb.flush_tlb_mva 0
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0
|
||||
system.cpu.dtb.flush_tlb_asid 0
|
||||
system.cpu.dtb.flush_entries 0
|
||||
system.cpu.dtb.align_faults 0
|
||||
system.cpu.dtb.prefetch_faults 0
|
||||
system.cpu.dtb.domain_faults 0
|
||||
system.cpu.dtb.perms_faults 0
|
||||
system.cpu.dtb.read_accesses 0
|
||||
system.cpu.dtb.write_accesses 0
|
||||
system.cpu.dtb.inst_accesses 0
|
||||
system.cpu.dtb.hits 0
|
||||
system.cpu.dtb.misses 0
|
||||
system.cpu.dtb.accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500
|
||||
system.cpu.itb.walker.walks 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.itb.inst_hits 0
|
||||
system.cpu.itb.inst_misses 0
|
||||
system.cpu.itb.read_hits 0
|
||||
system.cpu.itb.read_misses 0
|
||||
system.cpu.itb.write_hits 0
|
||||
system.cpu.itb.write_misses 0
|
||||
system.cpu.itb.flush_tlb 0
|
||||
system.cpu.itb.flush_tlb_mva 0
|
||||
system.cpu.itb.flush_tlb_mva_asid 0
|
||||
system.cpu.itb.flush_tlb_asid 0
|
||||
system.cpu.itb.flush_entries 0
|
||||
system.cpu.itb.align_faults 0
|
||||
system.cpu.itb.prefetch_faults 0
|
||||
system.cpu.itb.domain_faults 0
|
||||
system.cpu.itb.perms_faults 0
|
||||
system.cpu.itb.read_accesses 0
|
||||
system.cpu.itb.write_accesses 0
|
||||
system.cpu.itb.inst_accesses 0
|
||||
system.cpu.itb.hits 0
|
||||
system.cpu.itb.misses 0
|
||||
system.cpu.itb.accesses 0
|
||||
system.cpu.workload.numSyscalls 1946
|
||||
system.cpu.pwrStateResidencyTicks::ON 48960022500
|
||||
system.cpu.numCycles 97920046
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 70913204
|
||||
system.cpu.committedOps 90688159
|
||||
system.cpu.num_int_alu_accesses 81528528
|
||||
system.cpu.num_fp_alu_accesses 56
|
||||
system.cpu.num_func_calls 3311620
|
||||
system.cpu.num_conditional_control_insts 9253630
|
||||
system.cpu.num_int_insts 81528528
|
||||
system.cpu.num_fp_insts 56
|
||||
system.cpu.num_int_register_reads 141479271
|
||||
system.cpu.num_int_register_writes 53916335
|
||||
system.cpu.num_fp_register_reads 36
|
||||
system.cpu.num_fp_register_writes 20
|
||||
system.cpu.num_cc_register_reads 266608097
|
||||
system.cpu.num_cc_register_writes 36877111
|
||||
system.cpu.num_mem_refs 43422001
|
||||
system.cpu.num_load_insts 22866262
|
||||
system.cpu.num_store_insts 20555739
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 97920046
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 13741468
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00%
|
||||
system.cpu.op_class::IntAlu 47187979 52.03% 52.03%
|
||||
system.cpu.op_class::IntMult 80119 0.09% 52.12%
|
||||
system.cpu.op_class::IntDiv 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12%
|
||||
system.cpu.op_class::MemRead 22866242 25.21% 77.33%
|
||||
system.cpu.op_class::MemWrite 20555707 22.67% 100.00%
|
||||
system.cpu.op_class::FloatMemRead 20 0.00% 100.00%
|
||||
system.cpu.op_class::FloatMemWrite 32 0.00% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 90690106
|
||||
system.membus.snoop_filter.tot_requests 0
|
||||
system.membus.snoop_filter.hit_single_requests 0
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 48960022500
|
||||
system.membus.trans_dist::ReadReq 100925158
|
||||
system.membus.trans_dist::ReadResp 100941077
|
||||
system.membus.trans_dist::WriteReq 19849901
|
||||
system.membus.trans_dist::WriteResp 19849901
|
||||
system.membus.trans_dist::SoftPFReq 123744
|
||||
system.membus.trans_dist::SoftPFResp 123744
|
||||
system.membus.trans_dist::LoadLockedReq 15919
|
||||
system.membus.trans_dist::StoreCondReq 15919
|
||||
system.membus.trans_dist::StoreCondResp 15919
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100
|
||||
system.membus.pkt_count::total 241861282
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556
|
||||
system.membus.pkt_size::total 497813920
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 120930641
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 120930641 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 120930641
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,499 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=262144
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=131072
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
tag_latency=20
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
@@ -1,12 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 17:55:48
|
||||
gem5 started Apr 3 2017 17:56:13
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54226
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 128204299500 because exiting with last active thread context
|
||||
@@ -1,258 +0,0 @@
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
@@ -1,689 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.128204
|
||||
sim_ticks 128204299500
|
||||
final_tick 128204299500
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 533817
|
||||
host_op_rate 681535
|
||||
host_tick_rate 972489774
|
||||
host_mem_usage 290320
|
||||
host_seconds 131.83
|
||||
sim_insts 70373651
|
||||
sim_ops 89847385
|
||||
system.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.physmem.bytes_read::cpu.inst 233344
|
||||
system.physmem.bytes_read::cpu.data 7939200
|
||||
system.physmem.bytes_read::total 8172544
|
||||
system.physmem.bytes_inst_read::cpu.inst 233344
|
||||
system.physmem.bytes_inst_read::total 233344
|
||||
system.physmem.bytes_written::writebacks 5534528
|
||||
system.physmem.bytes_written::total 5534528
|
||||
system.physmem.num_reads::cpu.inst 3646
|
||||
system.physmem.num_reads::cpu.data 124050
|
||||
system.physmem.num_reads::total 127696
|
||||
system.physmem.num_writes::writebacks 86477
|
||||
system.physmem.num_writes::total 86477
|
||||
system.physmem.bw_read::cpu.inst 1820095
|
||||
system.physmem.bw_read::cpu.data 61926160
|
||||
system.physmem.bw_read::total 63746255
|
||||
system.physmem.bw_inst_read::cpu.inst 1820095
|
||||
system.physmem.bw_inst_read::total 1820095
|
||||
system.physmem.bw_write::writebacks 43169597
|
||||
system.physmem.bw_write::total 43169597
|
||||
system.physmem.bw_total::writebacks 43169597
|
||||
system.physmem.bw_total::cpu.inst 1820095
|
||||
system.physmem.bw_total::cpu.data 61926160
|
||||
system.physmem.bw_total::total 106915853
|
||||
system.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu_clk_domain.clock 500
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.dtb.walker.walks 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dtb.inst_hits 0
|
||||
system.cpu.dtb.inst_misses 0
|
||||
system.cpu.dtb.read_hits 0
|
||||
system.cpu.dtb.read_misses 0
|
||||
system.cpu.dtb.write_hits 0
|
||||
system.cpu.dtb.write_misses 0
|
||||
system.cpu.dtb.flush_tlb 0
|
||||
system.cpu.dtb.flush_tlb_mva 0
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0
|
||||
system.cpu.dtb.flush_tlb_asid 0
|
||||
system.cpu.dtb.flush_entries 0
|
||||
system.cpu.dtb.align_faults 0
|
||||
system.cpu.dtb.prefetch_faults 0
|
||||
system.cpu.dtb.domain_faults 0
|
||||
system.cpu.dtb.perms_faults 0
|
||||
system.cpu.dtb.read_accesses 0
|
||||
system.cpu.dtb.write_accesses 0
|
||||
system.cpu.dtb.inst_accesses 0
|
||||
system.cpu.dtb.hits 0
|
||||
system.cpu.dtb.misses 0
|
||||
system.cpu.dtb.accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.itb.walker.walks 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.itb.inst_hits 0
|
||||
system.cpu.itb.inst_misses 0
|
||||
system.cpu.itb.read_hits 0
|
||||
system.cpu.itb.read_misses 0
|
||||
system.cpu.itb.write_hits 0
|
||||
system.cpu.itb.write_misses 0
|
||||
system.cpu.itb.flush_tlb 0
|
||||
system.cpu.itb.flush_tlb_mva 0
|
||||
system.cpu.itb.flush_tlb_mva_asid 0
|
||||
system.cpu.itb.flush_tlb_asid 0
|
||||
system.cpu.itb.flush_entries 0
|
||||
system.cpu.itb.align_faults 0
|
||||
system.cpu.itb.prefetch_faults 0
|
||||
system.cpu.itb.domain_faults 0
|
||||
system.cpu.itb.perms_faults 0
|
||||
system.cpu.itb.read_accesses 0
|
||||
system.cpu.itb.write_accesses 0
|
||||
system.cpu.itb.inst_accesses 0
|
||||
system.cpu.itb.hits 0
|
||||
system.cpu.itb.misses 0
|
||||
system.cpu.itb.accesses 0
|
||||
system.cpu.workload.numSyscalls 1946
|
||||
system.cpu.pwrStateResidencyTicks::ON 128204299500
|
||||
system.cpu.numCycles 256408599
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 70373651
|
||||
system.cpu.committedOps 89847385
|
||||
system.cpu.num_int_alu_accesses 81528528
|
||||
system.cpu.num_fp_alu_accesses 56
|
||||
system.cpu.num_func_calls 3311620
|
||||
system.cpu.num_conditional_control_insts 9253630
|
||||
system.cpu.num_int_insts 81528528
|
||||
system.cpu.num_fp_insts 56
|
||||
system.cpu.num_int_register_reads 141328435
|
||||
system.cpu.num_int_register_writes 53916335
|
||||
system.cpu.num_fp_register_reads 36
|
||||
system.cpu.num_fp_register_writes 20
|
||||
system.cpu.num_cc_register_reads 334802072
|
||||
system.cpu.num_cc_register_writes 36877111
|
||||
system.cpu.num_mem_refs 43422001
|
||||
system.cpu.num_load_insts 22866262
|
||||
system.cpu.num_store_insts 20555739
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 256408599
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 13741468
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00%
|
||||
system.cpu.op_class::IntAlu 47187979 52.03% 52.03%
|
||||
system.cpu.op_class::IntMult 80119 0.09% 52.12%
|
||||
system.cpu.op_class::IntDiv 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 52.12%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12%
|
||||
system.cpu.op_class::MemRead 22866242 25.21% 77.33%
|
||||
system.cpu.op_class::MemWrite 20555707 22.67% 100.00%
|
||||
system.cpu.op_class::FloatMemRead 20 0.00% 100.00%
|
||||
system.cpu.op_class::FloatMemWrite 32 0.00% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 90690106
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.dcache.tags.replacements 155902
|
||||
system.cpu.dcache.tags.tagsinuse 4075.864194
|
||||
system.cpu.dcache.tags.total_refs 42601590
|
||||
system.cpu.dcache.tags.sampled_refs 159998
|
||||
system.cpu.dcache.tags.avg_refs 266.263266
|
||||
system.cpu.dcache.tags.warmup_cycle 1116590500
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995084
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995084
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 45
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 774
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1
|
||||
system.cpu.dcache.tags.tag_accesses 85731098
|
||||
system.cpu.dcache.tags.data_accesses 85731098
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 22743326
|
||||
system.cpu.dcache.ReadReq_hits::total 22743326
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19742869
|
||||
system.cpu.dcache.WriteReq_hits::total 19742869
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 83557
|
||||
system.cpu.dcache.SoftPFReq_hits::total 83557
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 15919
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919
|
||||
system.cpu.dcache.StoreCondReq_hits::total 15919
|
||||
system.cpu.dcache.demand_hits::cpu.data 42486195
|
||||
system.cpu.dcache.demand_hits::total 42486195
|
||||
system.cpu.dcache.overall_hits::cpu.data 42569752
|
||||
system.cpu.dcache.overall_hits::total 42569752
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 36741
|
||||
system.cpu.dcache.ReadReq_misses::total 36741
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 107032
|
||||
system.cpu.dcache.WriteReq_misses::total 107032
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 40187
|
||||
system.cpu.dcache.SoftPFReq_misses::total 40187
|
||||
system.cpu.dcache.demand_misses::cpu.data 143773
|
||||
system.cpu.dcache.demand_misses::total 143773
|
||||
system.cpu.dcache.overall_misses::cpu.data 183960
|
||||
system.cpu.dcache.overall_misses::total 183960
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 594992500
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 594992500
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6509368500
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 6509368500
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7104361000
|
||||
system.cpu.dcache.demand_miss_latency::total 7104361000
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7104361000
|
||||
system.cpu.dcache.overall_miss_latency::total 7104361000
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22780067
|
||||
system.cpu.dcache.ReadReq_accesses::total 22780067
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901
|
||||
system.cpu.dcache.WriteReq_accesses::total 19849901
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 123744
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 15919
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 15919
|
||||
system.cpu.dcache.demand_accesses::cpu.data 42629968
|
||||
system.cpu.dcache.demand_accesses::total 42629968
|
||||
system.cpu.dcache.overall_accesses::cpu.data 42753712
|
||||
system.cpu.dcache.overall_accesses::total 42753712
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001613
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001613
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005392
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324759
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.324759
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.003373
|
||||
system.cpu.dcache.demand_miss_rate::total 0.003373
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004303
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004303
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16194.238045
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.238045
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60817.031355
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60817.031355
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49413.735541
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 49413.735541
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38619.053055
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 38619.053055
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0
|
||||
system.cpu.dcache.blocked::no_mshrs 0
|
||||
system.cpu.dcache.blocked::no_targets 0
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.dcache.writebacks::writebacks 127926
|
||||
system.cpu.dcache.writebacks::total 127926
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7633
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 7633
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 7633
|
||||
system.cpu.dcache.demand_mshr_hits::total 7633
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 7633
|
||||
system.cpu.dcache.overall_mshr_hits::total 7633
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 29108
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 107032
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 23858
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 136140
|
||||
system.cpu.dcache.demand_mshr_misses::total 136140
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 159998
|
||||
system.cpu.dcache.overall_mshr_misses::total 159998
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 504199000
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 504199000
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6402336500
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6402336500
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1220892000
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1220892000
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6906535500
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6906535500
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8127427500
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8127427500
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003194
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17321.664147
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17321.664147
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59817.031355
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59817.031355
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51173.275212
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51173.275212
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.icache.tags.replacements 16890
|
||||
system.cpu.icache.tags.tagsinuse 1732.169683
|
||||
system.cpu.icache.tags.total_refs 78126184
|
||||
system.cpu.icache.tags.sampled_refs 18908
|
||||
system.cpu.icache.tags.avg_refs 4131.911572
|
||||
system.cpu.icache.tags.warmup_cycle 0
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1732.169683
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.845786
|
||||
system.cpu.icache.tags.occ_percent::total 0.845786
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2018
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 57
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 22
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 294
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1645
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.985352
|
||||
system.cpu.icache.tags.tag_accesses 156309092
|
||||
system.cpu.icache.tags.data_accesses 156309092
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 78126184
|
||||
system.cpu.icache.ReadReq_hits::total 78126184
|
||||
system.cpu.icache.demand_hits::cpu.inst 78126184
|
||||
system.cpu.icache.demand_hits::total 78126184
|
||||
system.cpu.icache.overall_hits::cpu.inst 78126184
|
||||
system.cpu.icache.overall_hits::total 78126184
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 18908
|
||||
system.cpu.icache.ReadReq_misses::total 18908
|
||||
system.cpu.icache.demand_misses::cpu.inst 18908
|
||||
system.cpu.icache.demand_misses::total 18908
|
||||
system.cpu.icache.overall_misses::cpu.inst 18908
|
||||
system.cpu.icache.overall_misses::total 18908
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 429951000
|
||||
system.cpu.icache.ReadReq_miss_latency::total 429951000
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 429951000
|
||||
system.cpu.icache.demand_miss_latency::total 429951000
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 429951000
|
||||
system.cpu.icache.overall_miss_latency::total 429951000
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 78145092
|
||||
system.cpu.icache.ReadReq_accesses::total 78145092
|
||||
system.cpu.icache.demand_accesses::cpu.inst 78145092
|
||||
system.cpu.icache.demand_accesses::total 78145092
|
||||
system.cpu.icache.overall_accesses::cpu.inst 78145092
|
||||
system.cpu.icache.overall_accesses::total 78145092
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000242
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000242
|
||||
system.cpu.icache.demand_miss_rate::total 0.000242
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000242
|
||||
system.cpu.icache.overall_miss_rate::total 0.000242
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.105141
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22739.105141
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.105141
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22739.105141
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.105141
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22739.105141
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.icache.blocked_cycles::no_targets 0
|
||||
system.cpu.icache.blocked::no_mshrs 0
|
||||
system.cpu.icache.blocked::no_targets 0
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.icache.writebacks::writebacks 16890
|
||||
system.cpu.icache.writebacks::total 16890
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 18908
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 18908
|
||||
system.cpu.icache.demand_mshr_misses::total 18908
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 18908
|
||||
system.cpu.icache.overall_mshr_misses::total 18908
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 411043000
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 411043000
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 411043000
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 411043000
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 411043000
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 411043000
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000242
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000242
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.105141
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.105141
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.l2cache.tags.replacements 96062
|
||||
system.cpu.l2cache.tags.tagsinuse 31698.825375
|
||||
system.cpu.l2cache.tags.total_refs 219067
|
||||
system.cpu.l2cache.tags.sampled_refs 128830
|
||||
system.cpu.l2cache.tags.avg_refs 1.700435
|
||||
system.cpu.l2cache.tags.warmup_cycle 20554489000
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 380.240484
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373230
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.211662
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011604
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.967371
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 798
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 14304
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 16713
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 1
|
||||
system.cpu.l2cache.tags.tag_accesses 2912846
|
||||
system.cpu.l2cache.tags.data_accesses 2912846
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 127926
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 127926
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 15790
|
||||
system.cpu.l2cache.WritebackClean_hits::total 15790
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 4712
|
||||
system.cpu.l2cache.ReadExReq_hits::total 4712
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15262
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 15262
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31236
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 31236
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 15262
|
||||
system.cpu.l2cache.demand_hits::cpu.data 35948
|
||||
system.cpu.l2cache.demand_hits::total 51210
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 15262
|
||||
system.cpu.l2cache.overall_hits::cpu.data 35948
|
||||
system.cpu.l2cache.overall_hits::total 51210
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 102320
|
||||
system.cpu.l2cache.ReadExReq_misses::total 102320
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3646
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 3646
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21730
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 21730
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3646
|
||||
system.cpu.l2cache.demand_misses::cpu.data 124050
|
||||
system.cpu.l2cache.demand_misses::total 127696
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3646
|
||||
system.cpu.l2cache.overall_misses::cpu.data 124050
|
||||
system.cpu.l2cache.overall_misses::total 127696
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6192310500
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6192310500
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 221047500
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 221047500
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1315278500
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1315278500
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 221047500
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7507589000
|
||||
system.cpu.l2cache.demand_miss_latency::total 7728636500
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 221047500
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7507589000
|
||||
system.cpu.l2cache.overall_miss_latency::total 7728636500
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 127926
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 127926
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 15790
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 15790
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 107032
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 18908
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 52966
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 18908
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 159998
|
||||
system.cpu.l2cache.demand_accesses::total 178906
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 18908
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 159998
|
||||
system.cpu.l2cache.overall_accesses::total 178906
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955976
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955976
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192828
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192828
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.410263
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.410263
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192828
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775322
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.713760
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192828
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775322
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.713760
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60519.062744
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60519.062744
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60627.399890
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60627.399890
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60528.232858
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60528.232858
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60627.399890
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60520.669085
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60523.716483
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60627.399890
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60520.669085
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60523.716483
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0
|
||||
system.cpu.l2cache.blocked::no_mshrs 0
|
||||
system.cpu.l2cache.blocked::no_targets 0
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.l2cache.writebacks::writebacks 86477
|
||||
system.cpu.l2cache.writebacks::total 86477
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 105
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102320
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 102320
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3646
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3646
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21730
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21730
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3646
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 124050
|
||||
system.cpu.l2cache.demand_mshr_misses::total 127696
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3646
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 124050
|
||||
system.cpu.l2cache.overall_mshr_misses::total 127696
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5169110500
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5169110500
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184587500
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184587500
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1097978500
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1097978500
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184587500
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6267089000
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6451676500
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184587500
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6267089000
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6451676500
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955976
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955976
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192828
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192828
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.410263
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.410263
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192828
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775322
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.713760
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192828
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775322
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.713760
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50519.062744
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50519.062744
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50627.399890
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50627.399890
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50528.232858
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50528.232858
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50627.399890
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50520.669085
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50523.716483
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50627.399890
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50520.669085
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50523.716483
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 351698
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 3224
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 71874
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 214403
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 16890
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 37561
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107032
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107032
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898
|
||||
system.cpu.toL2Bus.pkt_count::total 530604
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18427136
|
||||
system.cpu.toL2Bus.pkt_size::total 20718208
|
||||
system.cpu.toL2Bus.snoops 96062
|
||||
system.cpu.toL2Bus.snoopTraffic 5534528
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 274968
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.025367
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.157929
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.cpu.toL2Bus.snoop_fanout::0 268023 97.47% 97.47%
|
||||
system.cpu.toL2Bus.snoop_fanout::1 6915 2.51% 99.99%
|
||||
system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00%
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2
|
||||
system.cpu.toL2Bus.snoop_fanout::total 274968
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 320665000
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 28362000
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 239997000
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2
|
||||
system.membus.snoop_filter.tot_requests 220672
|
||||
system.membus.snoop_filter.hit_single_requests 93041
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500
|
||||
system.membus.trans_dist::ReadResp 25376
|
||||
system.membus.trans_dist::WritebackDirty 86477
|
||||
system.membus.trans_dist::CleanEvict 6466
|
||||
system.membus.trans_dist::ReadExReq 102320
|
||||
system.membus.trans_dist::ReadExResp 102320
|
||||
system.membus.trans_dist::ReadSharedReq 25376
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335
|
||||
system.membus.pkt_count::total 348335
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072
|
||||
system.membus.pkt_size::total 13707072
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 127704
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 127704 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 127704
|
||||
system.membus.reqLayer0.occupancy 569386372
|
||||
system.membus.reqLayer0.utilization 0.4
|
||||
system.membus.respLayer1.occupancy 638480000
|
||||
system.membus.respLayer1.utilization 0.5
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,213 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=SparcISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=vortex bendian.raw
|
||||
cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user