tests: Removed "tests/long"
Tests/resources contained within "tests/long" have been migrated to the testlib framework. Change-Id: I014edfac72f5d0df22abf4d4c7a69976b57d785a Issue-on: https://gem5.atlassian.net/browse/GEM5-109 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27630 Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Bobby R. Bruce
File diff suppressed because it is too large
Load Diff
@@ -1,66 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
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||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
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||||
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
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||||
warn: instruction 'mcr dccmvau' unimplemented
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||||
warn: instruction 'mcr icimvau' unimplemented
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||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
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||||
warn: instruction 'mcr dccimvac' unimplemented
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||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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warn: Not doing anything for miscreg ACTLR
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warn: Not doing anything for write of miscreg ACTLR
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warn: instruction 'mcr bpiall' unimplemented
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
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warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
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warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
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warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
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warn: Returning zero for read from miscreg pmcr
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warn: Ignoring write to miscreg pmcntenclr
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warn: Ignoring write to miscreg pmintenclr
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warn: Ignoring write to miscreg pmovsr
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warn: Ignoring write to miscreg pmcr
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warn: Ignoring write to miscreg pmcntenclr
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warn: Ignoring write to miscreg pmintenclr
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||||
warn: Ignoring write to miscreg pmovsr
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warn: Ignoring write to miscreg pmcr
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@@ -1,12 +0,0 @@
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Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simout
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Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Mar 29 2017 19:38:26
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gem5 started Mar 29 2017 19:38:42
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gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83600
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command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual
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Global frequency set at 1000000000000 ticks per second
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Exiting @ tick 2848623849000 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load Diff
@@ -1,214 +0,0 @@
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Booting Linux on physical CPU 0x0
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|
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Initializing cgroup subsys cpuset
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|
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Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
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Kernel was built at commit id ''
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CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
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CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
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Machine model: V2P-CA15
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||||
|
||||
bootconsole [earlycon0] enabled
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||||
|
||||
Memory policy: Data cache writealloc
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||||
|
||||
kdebugv2m: Following are test values to confirm proper working
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kdebugv2m: Ranges 42000000 0
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kdebugv2m: Regs 30000000 1000000
|
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|
||||
kdebugv2m: Virtual-Reg f0000000
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||||
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||||
kdebugv2m: pci node addr_cells 3
|
||||
|
||||
kdebugv2m: pci node size_cells 2
|
||||
|
||||
kdebugv2m: motherboard addr_cells 2
|
||||
|
||||
On node 0 totalpages: 65536
|
||||
|
||||
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
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||||
|
||||
Normal zone: 512 pages used for memmap
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||||
|
||||
Normal zone: 0 pages reserved
|
||||
|
||||
Normal zone: 65536 pages, LIFO batch:15
|
||||
|
||||
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
|
||||
|
||||
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
|
||||
|
||||
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
|
||||
|
||||
pcpu-alloc: [0] 0 [0] 1
|
||||
|
||||
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
|
||||
|
||||
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
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||||
|
||||
PID hash table entries: 1024 (order: 0, 4096 bytes)
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
|
||||
|
||||
Memory: 235656K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26488K reserved, 0K highmem)
|
||||
|
||||
Virtual kernel memory layout:
|
||||
|
||||
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
|
||||
|
||||
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
|
||||
|
||||
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
|
||||
|
||||
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
|
||||
|
||||
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
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||||
|
||||
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
|
||||
|
||||
.text : 0x80008000 - 0x806a942c (6790 kB)
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||||
|
||||
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
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||||
|
||||
.data : 0x806f4000 - 0x80732754 ( 250 kB)
|
||||
|
||||
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
|
||||
|
||||
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
|
||||
|
||||
Preemptible hierarchical RCU implementation.
|
||||
|
||||
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
|
||||
|
||||
NR_IRQS:16 nr_irqs:16 16
|
||||
|
||||
Architected cp15 timer(s) running at 25.16MHz (phys).
|
||||
|
||||
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
|
||||
|
||||
Switching to timer-based delay loop
|
||||
|
||||
Console: colour dummy device 80x30
|
||||
|
||||
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
|
||||
pid_max: default: 32768 minimum: 301
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
CPU: Testing write buffer coherency: ok
|
||||
|
||||
/cpus/cpu@1 missing clock-frequency property
|
||||
|
||||
CPU0: update cpu_power 1024
|
||||
|
||||
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
|
||||
|
||||
Setting up static identity map for 0x804fee68 - 0x804fee9c
|
||||
|
||||
CPU1: Booted secondary processor
|
||||
|
||||
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
|
||||
|
||||
Brought up 2 CPUs
|
||||
|
||||
SMP: Total of 2 processors activated.
|
||||
|
||||
CPU: All CPU(s) started in SVC mode.
|
||||
|
||||
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
DMA: preallocated 256 KiB pool for atomic coherent allocations
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: CPU 1 failed to disable vector catch
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
|
||||
|
||||
Serial: AMBA PL011 UART driver
|
||||
|
||||
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
|
||||
console [ttyAMA0] enabled
|
||||
console [ttyAMA0] enabled
|
||||
|
||||
bootconsole [earlycon0] disabled
|
||||
bootconsole [earlycon0] disabled
|
||||
|
||||
PCI host bridge to bus 0000:00
|
||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
PCI: bus0: Fast back to back transfers disabled
|
||||
pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
|
||||
pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
|
||||
pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
|
||||
pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
|
||||
pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
|
||||
pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
|
||||
PCI map irq: slot 0, pin 1, devslot 0, irq: 68
|
||||
PCI map irq: slot 1, pin 2, devslot 1, irq: 69
|
||||
bio: create slab <bio-0> at 0
|
||||
vgaarb: loaded
|
||||
SCSI subsystem initialized
|
||||
libata version 3.00 loaded.
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
pps_core: LinuxPPS API ver. 1 registered
|
||||
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
PTP clock support registered
|
||||
Advanced Linux Sound Architecture Driver Initialized.
|
||||
Switched to clocksource arch_sys_counter
|
||||
NET: Registered protocol family 2
|
||||
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
|
||||
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
TCP: Hash tables configured (established 2048 bind 2048)
|
||||
TCP: reno registered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,59 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
|
||||
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
|
||||
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
|
||||
warn: Returning zero for read from miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
@@ -1,12 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 29 2017 19:38:26
|
||||
gem5 started Mar 29 2017 19:38:42
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83599
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2854927627500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,208 +0,0 @@
|
||||
Booting Linux on physical CPU 0x0
|
||||
|
||||
Initializing cgroup subsys cpuset
|
||||
|
||||
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
|
||||
|
||||
Kernel was built at commit id ''
|
||||
|
||||
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
|
||||
|
||||
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
|
||||
|
||||
Machine model: V2P-CA15
|
||||
|
||||
bootconsole [earlycon0] enabled
|
||||
|
||||
Memory policy: Data cache writealloc
|
||||
|
||||
kdebugv2m: Following are test values to confirm proper working
|
||||
|
||||
kdebugv2m: Ranges 42000000 0
|
||||
|
||||
kdebugv2m: Regs 30000000 1000000
|
||||
|
||||
kdebugv2m: Virtual-Reg f0000000
|
||||
|
||||
kdebugv2m: pci node addr_cells 3
|
||||
|
||||
kdebugv2m: pci node size_cells 2
|
||||
|
||||
kdebugv2m: motherboard addr_cells 2
|
||||
|
||||
On node 0 totalpages: 65536
|
||||
|
||||
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
|
||||
|
||||
Normal zone: 512 pages used for memmap
|
||||
|
||||
Normal zone: 0 pages reserved
|
||||
|
||||
Normal zone: 65536 pages, LIFO batch:15
|
||||
|
||||
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
|
||||
|
||||
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
|
||||
|
||||
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
|
||||
|
||||
pcpu-alloc: [0] 0
|
||||
|
||||
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
|
||||
|
||||
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
|
||||
PID hash table entries: 1024 (order: 0, 4096 bytes)
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
|
||||
|
||||
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
|
||||
|
||||
Virtual kernel memory layout:
|
||||
|
||||
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
|
||||
|
||||
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
|
||||
|
||||
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
|
||||
|
||||
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
|
||||
|
||||
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
|
||||
|
||||
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
|
||||
|
||||
.text : 0x80008000 - 0x806a942c (6790 kB)
|
||||
|
||||
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
|
||||
|
||||
.data : 0x806f4000 - 0x80732754 ( 250 kB)
|
||||
|
||||
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
|
||||
|
||||
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
|
||||
|
||||
Preemptible hierarchical RCU implementation.
|
||||
|
||||
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
|
||||
|
||||
NR_IRQS:16 nr_irqs:16 16
|
||||
|
||||
Architected cp15 timer(s) running at 25.16MHz (phys).
|
||||
|
||||
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
|
||||
|
||||
Switching to timer-based delay loop
|
||||
|
||||
Console: colour dummy device 80x30
|
||||
|
||||
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
|
||||
pid_max: default: 32768 minimum: 301
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
CPU: Testing write buffer coherency: ok
|
||||
|
||||
CPU0: update cpu_power 1024
|
||||
|
||||
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
|
||||
|
||||
Setting up static identity map for 0x804fee68 - 0x804fee9c
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated.
|
||||
|
||||
CPU: All CPU(s) started in SVC mode.
|
||||
|
||||
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
DMA: preallocated 256 KiB pool for atomic coherent allocations
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: CPU 0 failed to disable vector catch
|
||||
|
||||
Serial: AMBA PL011 UART driver
|
||||
|
||||
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
|
||||
console [ttyAMA0] enabled
|
||||
console [ttyAMA0] enabled
|
||||
|
||||
bootconsole [earlycon0] disabled
|
||||
bootconsole [earlycon0] disabled
|
||||
|
||||
PCI host bridge to bus 0000:00
|
||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
PCI: bus0: Fast back to back transfers disabled
|
||||
pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
|
||||
pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
|
||||
pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
|
||||
pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
|
||||
pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
|
||||
pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
|
||||
PCI map irq: slot 0, pin 1, devslot 0, irq: 68
|
||||
PCI map irq: slot 1, pin 2, devslot 1, irq: 69
|
||||
bio: create slab <bio-0> at 0
|
||||
vgaarb: loaded
|
||||
SCSI subsystem initialized
|
||||
libata version 3.00 loaded.
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
pps_core: LinuxPPS API ver. 1 registered
|
||||
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
PTP clock support registered
|
||||
Advanced Linux Sound Architecture Driver Initialized.
|
||||
Switched to clocksource arch_sys_counter
|
||||
NET: Registered protocol family 2
|
||||
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
|
||||
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
TCP: Hash tables configured (established 2048 bind 2048)
|
||||
TCP: reno registered
|
||||
UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
NET: Registered protocol family 1
|
||||
RPC: Registered named UNIX socket transport module.
|
||||
RPC: Registered udp transport module.
|
||||
RPC: Registered tcp transport module.
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,68 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
warn: CP14 unimplemented crn[4], opc1[4], crm[0], opc2[0]
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
|
||||
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
|
||||
warn: allocating bonus target for snoop
|
||||
warn: allocating bonus target for snoop
|
||||
warn: Returning zero for read from miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
warn: instruction 'mcr dcisw' unimplemented
|
||||
@@ -1,12 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 29 2017 19:38:26
|
||||
gem5 started Mar 29 2017 19:38:42
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83601
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2826661822500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,214 +0,0 @@
|
||||
Booting Linux on physical CPU 0x0
|
||||
|
||||
Initializing cgroup subsys cpuset
|
||||
|
||||
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
|
||||
|
||||
Kernel was built at commit id ''
|
||||
|
||||
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
|
||||
|
||||
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
|
||||
|
||||
Machine model: V2P-CA15
|
||||
|
||||
bootconsole [earlycon0] enabled
|
||||
|
||||
Memory policy: Data cache writealloc
|
||||
|
||||
kdebugv2m: Following are test values to confirm proper working
|
||||
|
||||
kdebugv2m: Ranges 42000000 0
|
||||
|
||||
kdebugv2m: Regs 30000000 1000000
|
||||
|
||||
kdebugv2m: Virtual-Reg f0000000
|
||||
|
||||
kdebugv2m: pci node addr_cells 3
|
||||
|
||||
kdebugv2m: pci node size_cells 2
|
||||
|
||||
kdebugv2m: motherboard addr_cells 2
|
||||
|
||||
On node 0 totalpages: 65536
|
||||
|
||||
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
|
||||
|
||||
Normal zone: 512 pages used for memmap
|
||||
|
||||
Normal zone: 0 pages reserved
|
||||
|
||||
Normal zone: 65536 pages, LIFO batch:15
|
||||
|
||||
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
|
||||
|
||||
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
|
||||
|
||||
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
|
||||
|
||||
pcpu-alloc: [0] 0 [0] 1
|
||||
|
||||
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
|
||||
|
||||
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
|
||||
PID hash table entries: 1024 (order: 0, 4096 bytes)
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
|
||||
|
||||
Memory: 235656K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26488K reserved, 0K highmem)
|
||||
|
||||
Virtual kernel memory layout:
|
||||
|
||||
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
|
||||
|
||||
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
|
||||
|
||||
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
|
||||
|
||||
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
|
||||
|
||||
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
|
||||
|
||||
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
|
||||
|
||||
.text : 0x80008000 - 0x806a942c (6790 kB)
|
||||
|
||||
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
|
||||
|
||||
.data : 0x806f4000 - 0x80732754 ( 250 kB)
|
||||
|
||||
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
|
||||
|
||||
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
|
||||
|
||||
Preemptible hierarchical RCU implementation.
|
||||
|
||||
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
|
||||
|
||||
NR_IRQS:16 nr_irqs:16 16
|
||||
|
||||
Architected cp15 timer(s) running at 25.16MHz (phys).
|
||||
|
||||
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
|
||||
|
||||
Switching to timer-based delay loop
|
||||
|
||||
Console: colour dummy device 80x30
|
||||
|
||||
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
|
||||
pid_max: default: 32768 minimum: 301
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
CPU: Testing write buffer coherency: ok
|
||||
|
||||
/cpus/cpu@1 missing clock-frequency property
|
||||
|
||||
CPU0: update cpu_power 1024
|
||||
|
||||
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
|
||||
|
||||
Setting up static identity map for 0x804fee68 - 0x804fee9c
|
||||
|
||||
CPU1: Booted secondary processor
|
||||
|
||||
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
|
||||
|
||||
Brought up 2 CPUs
|
||||
|
||||
SMP: Total of 2 processors activated.
|
||||
|
||||
CPU: All CPU(s) started in SVC mode.
|
||||
|
||||
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
DMA: preallocated 256 KiB pool for atomic coherent allocations
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 1
|
||||
|
||||
hw-breakpoint: CPU 1 failed to disable vector catch
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
|
||||
|
||||
Serial: AMBA PL011 UART driver
|
||||
|
||||
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
|
||||
console [ttyAMA0] enabled
|
||||
console [ttyAMA0] enabled
|
||||
|
||||
bootconsole [earlycon0] disabled
|
||||
bootconsole [earlycon0] disabled
|
||||
|
||||
PCI host bridge to bus 0000:00
|
||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
PCI: bus0: Fast back to back transfers disabled
|
||||
pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
|
||||
pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
|
||||
pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
|
||||
pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
|
||||
pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
|
||||
pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
|
||||
PCI map irq: slot 0, pin 1, devslot 0, irq: 68
|
||||
PCI map irq: slot 1, pin 2, devslot 1, irq: 69
|
||||
bio: create slab <bio-0> at 0
|
||||
vgaarb: loaded
|
||||
SCSI subsystem initialized
|
||||
libata version 3.00 loaded.
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
pps_core: LinuxPPS API ver. 1 registered
|
||||
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
PTP clock support registered
|
||||
Advanced Linux Sound Architecture Driver Initialized.
|
||||
Switched to clocksource arch_sys_counter
|
||||
NET: Registered protocol family 2
|
||||
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
|
||||
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
TCP: Hash tables configured (established 2048 bind 2048)
|
||||
TCP: reno registered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,60 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
|
||||
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
|
||||
warn: Returning zero for read from miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
|
||||
warn: instruction 'mcr dcisw' unimplemented
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
@@ -1,12 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 29 2017 19:38:26
|
||||
gem5 started Mar 29 2017 19:38:42
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83598
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2829109393000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,208 +0,0 @@
|
||||
Booting Linux on physical CPU 0x0
|
||||
|
||||
Initializing cgroup subsys cpuset
|
||||
|
||||
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
|
||||
|
||||
Kernel was built at commit id ''
|
||||
|
||||
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
|
||||
|
||||
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
|
||||
|
||||
Machine model: V2P-CA15
|
||||
|
||||
bootconsole [earlycon0] enabled
|
||||
|
||||
Memory policy: Data cache writealloc
|
||||
|
||||
kdebugv2m: Following are test values to confirm proper working
|
||||
|
||||
kdebugv2m: Ranges 42000000 0
|
||||
|
||||
kdebugv2m: Regs 30000000 1000000
|
||||
|
||||
kdebugv2m: Virtual-Reg f0000000
|
||||
|
||||
kdebugv2m: pci node addr_cells 3
|
||||
|
||||
kdebugv2m: pci node size_cells 2
|
||||
|
||||
kdebugv2m: motherboard addr_cells 2
|
||||
|
||||
On node 0 totalpages: 65536
|
||||
|
||||
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
|
||||
|
||||
Normal zone: 512 pages used for memmap
|
||||
|
||||
Normal zone: 0 pages reserved
|
||||
|
||||
Normal zone: 65536 pages, LIFO batch:15
|
||||
|
||||
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
|
||||
|
||||
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
|
||||
|
||||
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
|
||||
|
||||
pcpu-alloc: [0] 0
|
||||
|
||||
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
|
||||
|
||||
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
|
||||
PID hash table entries: 1024 (order: 0, 4096 bytes)
|
||||
|
||||
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
|
||||
|
||||
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
|
||||
|
||||
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
|
||||
|
||||
Virtual kernel memory layout:
|
||||
|
||||
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
|
||||
|
||||
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
|
||||
|
||||
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
|
||||
|
||||
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
|
||||
|
||||
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
|
||||
|
||||
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
|
||||
|
||||
.text : 0x80008000 - 0x806a942c (6790 kB)
|
||||
|
||||
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
|
||||
|
||||
.data : 0x806f4000 - 0x80732754 ( 250 kB)
|
||||
|
||||
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
|
||||
|
||||
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
|
||||
|
||||
Preemptible hierarchical RCU implementation.
|
||||
|
||||
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
|
||||
|
||||
NR_IRQS:16 nr_irqs:16 16
|
||||
|
||||
Architected cp15 timer(s) running at 25.16MHz (phys).
|
||||
|
||||
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
|
||||
|
||||
Switching to timer-based delay loop
|
||||
|
||||
Console: colour dummy device 80x30
|
||||
|
||||
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
|
||||
pid_max: default: 32768 minimum: 301
|
||||
|
||||
Mount-cache hash table entries: 512
|
||||
|
||||
CPU: Testing write buffer coherency: ok
|
||||
|
||||
CPU0: update cpu_power 1024
|
||||
|
||||
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
|
||||
|
||||
Setting up static identity map for 0x804fee68 - 0x804fee9c
|
||||
|
||||
Brought up 1 CPUs
|
||||
|
||||
SMP: Total of 1 processors activated.
|
||||
|
||||
CPU: All CPU(s) started in SVC mode.
|
||||
|
||||
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
|
||||
|
||||
NET: Registered protocol family 16
|
||||
|
||||
DMA: preallocated 256 KiB pool for atomic coherent allocations
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
|
||||
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
|
||||
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
|
||||
|
||||
hw-breakpoint: CPU 0 failed to disable vector catch
|
||||
|
||||
Serial: AMBA PL011 UART driver
|
||||
|
||||
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
|
||||
console [ttyAMA0] enabled
|
||||
console [ttyAMA0] enabled
|
||||
|
||||
bootconsole [earlycon0] disabled
|
||||
bootconsole [earlycon0] disabled
|
||||
|
||||
PCI host bridge to bus 0000:00
|
||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
|
||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
PCI: bus0: Fast back to back transfers disabled
|
||||
pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
|
||||
pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
|
||||
pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
|
||||
pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
|
||||
pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
|
||||
pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
|
||||
pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
|
||||
PCI map irq: slot 0, pin 1, devslot 0, irq: 68
|
||||
PCI map irq: slot 1, pin 2, devslot 1, irq: 69
|
||||
bio: create slab <bio-0> at 0
|
||||
vgaarb: loaded
|
||||
SCSI subsystem initialized
|
||||
libata version 3.00 loaded.
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
pps_core: LinuxPPS API ver. 1 registered
|
||||
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
PTP clock support registered
|
||||
Advanced Linux Sound Architecture Driver Initialized.
|
||||
Switched to clocksource arch_sys_counter
|
||||
NET: Registered protocol family 2
|
||||
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
|
||||
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
TCP: Hash tables configured (established 2048 bind 2048)
|
||||
TCP: reno registered
|
||||
UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
NET: Registered protocol family 1
|
||||
RPC: Registered named UNIX socket transport module.
|
||||
RPC: Registered udp transport module.
|
||||
RPC: Registered tcp transport module.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,13 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
@@ -1,18 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 11 2016 00:00:58
|
||||
gem5 started Oct 13 2016 20:43:00
|
||||
gem5 executing on e108600-lin, pid 17333
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor-dual
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 47554910274000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,183 +0,0 @@
|
||||
[ 0.000000] Initializing cgroup subsys cpu
|
||||
[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
|
||||
[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
|
||||
[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
|
||||
[ 0.000000] Memory limited to 256MB
|
||||
[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
|
||||
[ 0.000000] On node 0 totalpages: 65536
|
||||
[ 0.000000] DMA zone: 896 pages used for memmap
|
||||
[ 0.000000] DMA zone: 0 pages reserved
|
||||
[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
|
||||
[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
|
||||
[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
|
||||
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
|
||||
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
|
||||
[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
|
||||
[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
|
||||
[ 0.000000] Virtual kernel memory layout:
|
||||
[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
|
||||
[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
|
||||
[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
|
||||
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
|
||||
[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
|
||||
[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
|
||||
[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
|
||||
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
[ 0.000000] Preemptible hierarchical RCU implementation.
|
||||
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
|
||||
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000024] Console: colour dummy device 80x25
|
||||
[ 0.000027] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000028] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000039] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000040] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000160] hw perfevents: no hardware support available
|
||||
[ 0.060042] CPU1: Booted secondary processor
|
||||
[ 1.080079] CPU2: failed to come online
|
||||
[ 2.100148] CPU3: failed to come online
|
||||
[ 2.100151] Brought up 2 CPUs
|
||||
[ 2.100152] SMP: Total of 2 processors activated.
|
||||
[ 2.100226] devtmpfs: initialized
|
||||
[ 2.100728] atomic64_test: passed
|
||||
[ 2.100773] regulator-dummy: no parameters
|
||||
[ 2.101119] NET: Registered protocol family 16
|
||||
[ 2.101251] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 2.101259] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 2.101662] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 2.101665] Serial: AMBA PL011 UART driver
|
||||
[ 2.101855] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 2.101892] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 2.102468] console [ttyAMA0] enabled
|
||||
[ 2.102623] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 2.102687] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 2.102745] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 2.102803] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 2.140306] 3V3: 3300 mV
|
||||
[ 2.140354] vgaarb: loaded
|
||||
[ 2.140400] SCSI subsystem initialized
|
||||
[ 2.140435] libata version 3.00 loaded.
|
||||
[ 2.140482] usbcore: registered new interface driver usbfs
|
||||
[ 2.140500] usbcore: registered new interface driver hub
|
||||
[ 2.140526] usbcore: registered new device driver usb
|
||||
[ 2.140554] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 2.140564] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 2.140583] PTP clock support registered
|
||||
[ 2.140715] Switched to clocksource arch_sys_counter
|
||||
[ 2.142179] NET: Registered protocol family 2
|
||||
[ 2.142255] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 2.142273] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 2.142290] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 2.142312] TCP: reno registered
|
||||
[ 2.142319] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.142331] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.142367] NET: Registered protocol family 1
|
||||
[ 2.142431] RPC: Registered named UNIX socket transport module.
|
||||
[ 2.142441] RPC: Registered udp transport module.
|
||||
[ 2.142450] RPC: Registered tcp transport module.
|
||||
[ 2.142458] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 2.142471] PCI: CLS 0 bytes, default 64
|
||||
[ 2.142634] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 2.142729] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 2.144357] fuse init (API version 7.23)
|
||||
[ 2.144445] msgmni has been set to 469
|
||||
[ 2.144792] io scheduler noop registered
|
||||
[ 2.144847] io scheduler cfq registered (default)
|
||||
[ 2.145229] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.145243] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.145255] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.145268] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.145278] pci_bus 0000:00: scanning bus
|
||||
[ 2.145289] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.145303] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 2.145317] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.145353] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 2.145366] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.145377] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.145388] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.145399] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.145410] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.145421] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.145456] pci_bus 0000:00: fixups for bus
|
||||
[ 2.145464] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 2.145476] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 2.145496] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 2.145505] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 2.145516] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 2.145525] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 2.145537] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 2.145551] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 2.145564] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 2.145577] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 2.145589] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 2.145601] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 2.145612] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 2.145624] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 2.146092] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 2.146340] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 2.146352] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 2.146375] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 2.146628] scsi0 : ata_piix
|
||||
[ 2.146701] scsi1 : ata_piix
|
||||
[ 2.146733] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 2.146746] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 2.146850] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 2.146863] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.146877] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.146889] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.300748] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.300759] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.300788] ata1.00: configured for UDMA/33
|
||||
[ 2.300844] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.300954] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.300958] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.300986] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.300996] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.301021] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.301150] sda: sda1
|
||||
[ 2.301268] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.421014] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.421028] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.421050] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 2.421060] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 2.421081] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 2.421093] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 2.421166] usbcore: registered new interface driver usb-storage
|
||||
[ 2.421232] mousedev: PS/2 mouse device common for all mice
|
||||
[ 2.421395] usbcore: registered new interface driver usbhid
|
||||
[ 2.421405] usbhid: USB HID core driver
|
||||
[ 2.421435] TCP: cubic registered
|
||||
[ 2.421443] NET: Registered protocol family 17
|
||||
[ 2.421846] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 2.421896] devtmpfs: mounted
|
||||
[ 2.421929] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
|
||||
INIT: version 2.88 booting
|
||||
|
||||
Starting udev
|
||||
[ 2.460465] udevd[609]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
|
||||
[ 2.543480] random: dd urandom read with 18 bits of entropy available
|
||||
Populating dev cache
|
||||
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
Mon Jan 27 08:00:00 UTC 2014
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
|
||||
INIT: Entering runlevel: 5
|
||||
|
||||
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,12 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
@@ -1,18 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 11 2016 00:00:58
|
||||
gem5 started Oct 13 2016 21:01:48
|
||||
gem5 executing on e108600-lin, pid 17560
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 51688774990000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,183 +0,0 @@
|
||||
[ 0.000000] Initializing cgroup subsys cpu
|
||||
[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
|
||||
[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
|
||||
[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
|
||||
[ 0.000000] Memory limited to 256MB
|
||||
[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
|
||||
[ 0.000000] On node 0 totalpages: 65536
|
||||
[ 0.000000] DMA zone: 896 pages used for memmap
|
||||
[ 0.000000] DMA zone: 0 pages reserved
|
||||
[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
|
||||
[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
|
||||
[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
|
||||
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
|
||||
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
|
||||
[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
|
||||
[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
|
||||
[ 0.000000] Virtual kernel memory layout:
|
||||
[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
|
||||
[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
|
||||
[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
|
||||
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
|
||||
[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
|
||||
[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
|
||||
[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
|
||||
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
[ 0.000000] Preemptible hierarchical RCU implementation.
|
||||
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
|
||||
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000027] Console: colour dummy device 80x25
|
||||
[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000032] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000181] hw perfevents: no hardware support available
|
||||
[ 1.060097] CPU1: failed to come online
|
||||
[ 2.080187] CPU2: failed to come online
|
||||
[ 3.100278] CPU3: failed to come online
|
||||
[ 3.100281] Brought up 1 CPUs
|
||||
[ 3.100283] SMP: Total of 1 processors activated.
|
||||
[ 3.100354] devtmpfs: initialized
|
||||
[ 3.100991] atomic64_test: passed
|
||||
[ 3.101046] regulator-dummy: no parameters
|
||||
[ 3.101555] NET: Registered protocol family 16
|
||||
[ 3.101721] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.101732] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.102038] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.102043] Serial: AMBA PL011 UART driver
|
||||
[ 3.102290] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.102335] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.102901] console [ttyAMA0] enabled
|
||||
[ 3.103000] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.103038] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.103076] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.103112] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130703] 3V3: 3300 mV
|
||||
[ 3.130755] vgaarb: loaded
|
||||
[ 3.130815] SCSI subsystem initialized
|
||||
[ 3.130867] libata version 3.00 loaded.
|
||||
[ 3.130924] usbcore: registered new interface driver usbfs
|
||||
[ 3.130945] usbcore: registered new interface driver hub
|
||||
[ 3.130986] usbcore: registered new device driver usb
|
||||
[ 3.131018] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.131027] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.131047] PTP clock support registered
|
||||
[ 3.131197] Switched to clocksource arch_sys_counter
|
||||
[ 3.132637] NET: Registered protocol family 2
|
||||
[ 3.132735] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.132757] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.132784] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.132801] TCP: reno registered
|
||||
[ 3.132809] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132824] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132871] NET: Registered protocol family 1
|
||||
[ 3.132921] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.132932] RPC: Registered udp transport module.
|
||||
[ 3.132940] RPC: Registered tcp transport module.
|
||||
[ 3.132948] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.132961] PCI: CLS 0 bytes, default 64
|
||||
[ 3.133158] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.133307] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.135503] fuse init (API version 7.23)
|
||||
[ 3.135611] msgmni has been set to 469
|
||||
[ 3.138767] io scheduler noop registered
|
||||
[ 3.138836] io scheduler cfq registered (default)
|
||||
[ 3.139309] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.139322] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.139334] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.139347] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.139357] pci_bus 0000:00: scanning bus
|
||||
[ 3.139369] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.139383] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.139398] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.139443] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.139455] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.139467] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.139478] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.139489] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.139501] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.139513] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.139555] pci_bus 0000:00: fixups for bus
|
||||
[ 3.139564] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.139576] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.139598] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.139607] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.139619] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.139628] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.139641] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.139654] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.139668] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.139681] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.139693] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.139705] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.139717] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.139729] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.140375] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.140706] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.140717] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.140741] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.141104] scsi0 : ata_piix
|
||||
[ 3.141497] scsi1 : ata_piix
|
||||
[ 3.141534] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.141547] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.141673] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.141686] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.141703] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.141715] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.301229] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.301240] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.301271] ata1.00: configured for UDMA/33
|
||||
[ 3.301328] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.301469] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.301499] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.301548] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.301558] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.301583] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.301736] sda: sda1
|
||||
[ 3.301887] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.421517] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.421531] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.421555] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.421565] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.421589] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.421601] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.421690] usbcore: registered new interface driver usb-storage
|
||||
[ 3.421758] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.421951] usbcore: registered new interface driver usbhid
|
||||
[ 3.421962] usbhid: USB HID core driver
|
||||
[ 3.421997] TCP: cubic registered
|
||||
[ 3.422006] NET: Registered protocol family 17
|
||||
[ 3.422432] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.422472] devtmpfs: mounted
|
||||
[ 3.422501] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
|
||||
INIT: version 2.88 booting
|
||||
|
||||
Starting udev
|
||||
[ 3.464513] udevd[607]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
|
||||
[ 3.604760] random: dd urandom read with 21 bits of entropy available
|
||||
Populating dev cache
|
||||
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
Mon Jan 27 08:00:00 UTC 2014
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
|
||||
INIT: Entering runlevel: 5
|
||||
|
||||
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,16 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: allocating bonus target for snoop
|
||||
warn: allocating bonus target for snoop
|
||||
warn: allocating bonus target for snoop
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
@@ -1,18 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 11 2016 00:00:58
|
||||
gem5 started Oct 13 2016 20:43:00
|
||||
gem5 executing on e108600-lin, pid 17330
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-dual
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 47384942719000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,184 +0,0 @@
|
||||
[ 0.000000] Initializing cgroup subsys cpu
|
||||
[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
|
||||
[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
|
||||
[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
|
||||
[ 0.000000] Memory limited to 256MB
|
||||
[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
|
||||
[ 0.000000] On node 0 totalpages: 65536
|
||||
[ 0.000000] DMA zone: 896 pages used for memmap
|
||||
[ 0.000000] DMA zone: 0 pages reserved
|
||||
[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
|
||||
[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
|
||||
[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
|
||||
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
|
||||
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
|
||||
[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
|
||||
[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
|
||||
[ 0.000000] Virtual kernel memory layout:
|
||||
[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
|
||||
[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
|
||||
[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
|
||||
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
|
||||
[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
|
||||
[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
|
||||
[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
|
||||
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
[ 0.000000] Preemptible hierarchical RCU implementation.
|
||||
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
|
||||
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000015] Console: colour dummy device 80x25
|
||||
[ 0.000017] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000018] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000025] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000026] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000102] hw perfevents: no hardware support available
|
||||
[ 0.060026] CPU1: Booted secondary processor
|
||||
[ 1.080049] CPU2: failed to come online
|
||||
[ 2.100093] CPU3: failed to come online
|
||||
[ 2.100095] Brought up 2 CPUs
|
||||
[ 2.100096] SMP: Total of 2 processors activated.
|
||||
[ 2.100135] devtmpfs: initialized
|
||||
[ 2.100443] atomic64_test: passed
|
||||
[ 2.100471] regulator-dummy: no parameters
|
||||
[ 2.100695] NET: Registered protocol family 16
|
||||
[ 2.100778] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 2.100785] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 2.100927] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 2.100930] Serial: AMBA PL011 UART driver
|
||||
[ 2.101048] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 2.101072] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 2.101655] console [ttyAMA0] enabled
|
||||
[ 2.101721] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 2.101750] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 2.101779] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 2.101807] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 2.140200] 3V3: 3300 mV
|
||||
[ 2.140234] vgaarb: loaded
|
||||
[ 2.140266] SCSI subsystem initialized
|
||||
[ 2.140287] libata version 3.00 loaded.
|
||||
[ 2.140319] usbcore: registered new interface driver usbfs
|
||||
[ 2.140334] usbcore: registered new interface driver hub
|
||||
[ 2.140351] usbcore: registered new device driver usb
|
||||
[ 2.140371] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 2.140380] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 2.140398] PTP clock support registered
|
||||
[ 2.140483] Switched to clocksource arch_sys_counter
|
||||
[ 2.141317] NET: Registered protocol family 2
|
||||
[ 2.141370] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 2.141386] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 2.141401] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 2.141417] TCP: reno registered
|
||||
[ 2.141424] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.141435] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.141463] NET: Registered protocol family 1
|
||||
[ 2.141503] RPC: Registered named UNIX socket transport module.
|
||||
[ 2.141513] RPC: Registered udp transport module.
|
||||
[ 2.141522] RPC: Registered tcp transport module.
|
||||
[ 2.141530] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 2.141542] PCI: CLS 0 bytes, default 64
|
||||
[ 2.141648] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 2.141718] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 2.142752] fuse init (API version 7.23)
|
||||
[ 2.142809] msgmni has been set to 469
|
||||
[ 2.142890] io scheduler noop registered
|
||||
[ 2.142925] io scheduler cfq registered (default)
|
||||
[ 2.143148] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.143161] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.143172] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.143184] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.143195] pci_bus 0000:00: scanning bus
|
||||
[ 2.143204] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.143217] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 2.143231] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.143258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 2.143270] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.143280] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.143291] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.143302] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.143312] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.143323] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.143351] pci_bus 0000:00: fixups for bus
|
||||
[ 2.143359] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 2.143371] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 2.143388] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 2.143397] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 2.143406] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 2.143415] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 2.143425] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 2.143438] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 2.143451] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 2.143463] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 2.143475] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 2.143486] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 2.143497] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 2.143509] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 2.143798] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 2.143959] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 2.143970] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 2.143987] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 2.144155] scsi0 : ata_piix
|
||||
[ 2.144211] scsi1 : ata_piix
|
||||
[ 2.144232] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 2.144244] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 2.144315] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 2.144327] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.144340] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.144352] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.300506] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.300516] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.300541] ata1.00: configured for UDMA/33
|
||||
[ 2.300579] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.300655] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.300670] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.300700] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.300709] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.300725] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.300818] sda: sda1
|
||||
[ 2.300900] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.420759] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.420772] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.420790] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 2.420801] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 2.420818] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 2.420830] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 2.420879] usbcore: registered new interface driver usb-storage
|
||||
[ 2.420923] mousedev: PS/2 mouse device common for all mice
|
||||
[ 2.421032] usbcore: registered new interface driver usbhid
|
||||
[ 2.421042] usbhid: USB HID core driver
|
||||
[ 2.421068] TCP: cubic registered
|
||||
[ 2.421076] NET: Registered protocol family 17
|
||||
[ 2.421334] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 2.421363] devtmpfs: mounted
|
||||
[ 2.421381] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
|
||||
INIT: version 2.88 booting
|
||||
|
||||
Starting udev
|
||||
[ 2.457503] udevd[609]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
|
||||
[ 2.532427] random: dd urandom read with 18 bits of entropy available
|
||||
Populating dev cache
|
||||
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
Mon Jan 27 08:00:00 UTC 2014
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
|
||||
INIT: Entering runlevel: 5
|
||||
|
||||
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,12 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
@@ -1,18 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 11 2016 00:00:58
|
||||
gem5 started Oct 13 2016 21:05:44
|
||||
gem5 executing on e108600-lin, pid 17601
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 51558697863000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,183 +0,0 @@
|
||||
[ 0.000000] Initializing cgroup subsys cpu
|
||||
[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
|
||||
[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
|
||||
[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
|
||||
[ 0.000000] Memory limited to 256MB
|
||||
[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
|
||||
[ 0.000000] On node 0 totalpages: 65536
|
||||
[ 0.000000] DMA zone: 896 pages used for memmap
|
||||
[ 0.000000] DMA zone: 0 pages reserved
|
||||
[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
|
||||
[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
|
||||
[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
|
||||
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
|
||||
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
|
||||
[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
|
||||
[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
|
||||
[ 0.000000] Virtual kernel memory layout:
|
||||
[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
|
||||
[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
|
||||
[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
|
||||
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
|
||||
[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
|
||||
[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
|
||||
[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
|
||||
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
[ 0.000000] Preemptible hierarchical RCU implementation.
|
||||
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
|
||||
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000019] Console: colour dummy device 80x25
|
||||
[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000022] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000032] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000033] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000120] hw perfevents: no hardware support available
|
||||
[ 1.060065] CPU1: failed to come online
|
||||
[ 2.080126] CPU2: failed to come online
|
||||
[ 3.100188] CPU3: failed to come online
|
||||
[ 3.100190] Brought up 1 CPUs
|
||||
[ 3.100191] SMP: Total of 1 processors activated.
|
||||
[ 3.100238] devtmpfs: initialized
|
||||
[ 3.100663] atomic64_test: passed
|
||||
[ 3.100701] regulator-dummy: no parameters
|
||||
[ 3.101063] NET: Registered protocol family 16
|
||||
[ 3.101179] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.101187] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.101343] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.101347] Serial: AMBA PL011 UART driver
|
||||
[ 3.101513] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.101543] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.102115] console [ttyAMA0] enabled
|
||||
[ 3.102184] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.102216] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.102248] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.102278] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130478] 3V3: 3300 mV
|
||||
[ 3.130515] vgaarb: loaded
|
||||
[ 3.130558] SCSI subsystem initialized
|
||||
[ 3.130595] libata version 3.00 loaded.
|
||||
[ 3.130635] usbcore: registered new interface driver usbfs
|
||||
[ 3.130652] usbcore: registered new interface driver hub
|
||||
[ 3.130683] usbcore: registered new device driver usb
|
||||
[ 3.130706] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.130716] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.130734] PTP clock support registered
|
||||
[ 3.130840] Switched to clocksource arch_sys_counter
|
||||
[ 3.131799] NET: Registered protocol family 2
|
||||
[ 3.131866] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.131883] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.131902] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.131917] TCP: reno registered
|
||||
[ 3.131924] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.131937] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.131972] NET: Registered protocol family 1
|
||||
[ 3.132017] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.132028] RPC: Registered udp transport module.
|
||||
[ 3.132036] RPC: Registered tcp transport module.
|
||||
[ 3.132044] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.132057] PCI: CLS 0 bytes, default 64
|
||||
[ 3.132193] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.132284] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.133790] fuse init (API version 7.23)
|
||||
[ 3.133866] msgmni has been set to 469
|
||||
[ 3.135967] io scheduler noop registered
|
||||
[ 3.136016] io scheduler cfq registered (default)
|
||||
[ 3.136336] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.136349] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.136360] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.136373] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.136383] pci_bus 0000:00: scanning bus
|
||||
[ 3.136393] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.136406] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.136420] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.136454] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.136466] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.136477] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.136488] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.136499] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.136510] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.136521] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.136554] pci_bus 0000:00: fixups for bus
|
||||
[ 3.136562] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.136574] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.136592] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.136601] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.136611] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.136620] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.136631] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.136644] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.136657] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.136670] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.136682] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.136693] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.136705] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.136716] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.137147] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.137373] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.137384] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.137403] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.137653] scsi0 : ata_piix
|
||||
[ 3.137740] scsi1 : ata_piix
|
||||
[ 3.137768] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.137780] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.137872] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.137884] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.137899] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.137911] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.290863] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.290873] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.290899] ata1.00: configured for UDMA/33
|
||||
[ 3.290941] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.291042] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.291065] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.291102] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.291112] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.291131] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.291239] sda: sda1
|
||||
[ 3.291342] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.411129] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.411142] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.411163] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.411173] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.411193] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.411205] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.411268] usbcore: registered new interface driver usb-storage
|
||||
[ 3.411318] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.411454] usbcore: registered new interface driver usbhid
|
||||
[ 3.411464] usbhid: USB HID core driver
|
||||
[ 3.411492] TCP: cubic registered
|
||||
[ 3.411499] NET: Registered protocol family 17
|
||||
[ 3.411807] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.411840] devtmpfs: mounted
|
||||
[ 3.411860] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
|
||||
INIT: version 2.88 booting
|
||||
|
||||
Starting udev
|
||||
[ 3.450256] udevd[607]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
|
||||
[ 3.603394] random: dd urandom read with 21 bits of entropy available
|
||||
Populating dev cache
|
||||
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
Mon Jan 27 08:00:00 UTC 2014
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
|
||||
INIT: Entering runlevel: 5
|
||||
|
||||
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,13 +0,0 @@
|
||||
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
@@ -1,18 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:49:27
|
||||
gem5 executing on e108600-lin, pid 23294
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 47296281748500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,184 +0,0 @@
|
||||
[ 0.000000] Initializing cgroup subsys cpu
|
||||
[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
|
||||
[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
|
||||
[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
|
||||
[ 0.000000] Memory limited to 256MB
|
||||
[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
|
||||
[ 0.000000] On node 0 totalpages: 65536
|
||||
[ 0.000000] DMA zone: 896 pages used for memmap
|
||||
[ 0.000000] DMA zone: 0 pages reserved
|
||||
[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
|
||||
[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
|
||||
[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
|
||||
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
|
||||
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
|
||||
[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
|
||||
[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
|
||||
[ 0.000000] Virtual kernel memory layout:
|
||||
[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
|
||||
[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
|
||||
[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
|
||||
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
|
||||
[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
|
||||
[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
|
||||
[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
|
||||
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
[ 0.000000] Preemptible hierarchical RCU implementation.
|
||||
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
|
||||
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000013] Console: colour dummy device 80x25
|
||||
[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000015] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000066] hw perfevents: no hardware support available
|
||||
[ 0.060015] CPU1: Booted secondary processor
|
||||
[ 1.080050] CPU2: failed to come online
|
||||
[ 2.100100] CPU3: failed to come online
|
||||
[ 2.100101] Brought up 2 CPUs
|
||||
[ 2.100102] SMP: Total of 2 processors activated.
|
||||
[ 2.100134] devtmpfs: initialized
|
||||
[ 2.100536] atomic64_test: passed
|
||||
[ 2.100559] regulator-dummy: no parameters
|
||||
[ 2.100800] NET: Registered protocol family 16
|
||||
[ 2.100894] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 2.100898] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 2.100937] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 2.100938] Serial: AMBA PL011 UART driver
|
||||
[ 2.101059] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 2.101082] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 2.101116] console [ttyAMA0] enabled
|
||||
[ 2.101154] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 2.101168] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 2.101183] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 2.101195] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 2.140179] 3V3: 3300 mV
|
||||
[ 2.140202] vgaarb: loaded
|
||||
[ 2.140232] SCSI subsystem initialized
|
||||
[ 2.140246] libata version 3.00 loaded.
|
||||
[ 2.140272] usbcore: registered new interface driver usbfs
|
||||
[ 2.140279] usbcore: registered new interface driver hub
|
||||
[ 2.140288] usbcore: registered new device driver usb
|
||||
[ 2.140300] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 2.140301] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 2.140304] PTP clock support registered
|
||||
[ 2.140381] Switched to clocksource arch_sys_counter
|
||||
[ 2.141215] NET: Registered protocol family 2
|
||||
[ 2.141272] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 2.141277] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 2.141282] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 2.141285] TCP: reno registered
|
||||
[ 2.141286] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.141288] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.141303] NET: Registered protocol family 1
|
||||
[ 2.141330] RPC: Registered named UNIX socket transport module.
|
||||
[ 2.141331] RPC: Registered udp transport module.
|
||||
[ 2.141331] RPC: Registered tcp transport module.
|
||||
[ 2.141332] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 2.141334] PCI: CLS 0 bytes, default 64
|
||||
[ 2.141433] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 2.141477] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 2.143024] fuse init (API version 7.23)
|
||||
[ 2.143091] msgmni has been set to 469
|
||||
[ 2.143142] io scheduler noop registered
|
||||
[ 2.143175] io scheduler cfq registered (default)
|
||||
[ 2.143447] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.143448] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.143450] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.143452] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.143453] pci_bus 0000:00: scanning bus
|
||||
[ 2.143455] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.143457] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 2.143460] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.143476] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 2.143477] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.143479] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.143481] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.143483] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.143484] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.143486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.143503] pci_bus 0000:00: fixups for bus
|
||||
[ 2.143505] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 2.143506] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 2.143511] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 2.143512] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 2.143515] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 2.143516] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 2.143519] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 2.143520] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 2.143522] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 2.143524] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 2.143525] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 2.143527] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 2.143529] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 2.143531] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 2.143891] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 2.144060] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 2.144062] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 2.144068] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 2.144250] scsi0 : ata_piix
|
||||
[ 2.144297] scsi1 : ata_piix
|
||||
[ 2.144314] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 2.144315] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 2.144376] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 2.144377] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.144381] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.144382] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.290387] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.290388] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.290395] ata1.00: configured for UDMA/33
|
||||
[ 2.290411] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.290465] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.290468] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.290484] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.290485] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.290492] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.290547] sda: sda1
|
||||
[ 2.290609] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.410644] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.410646] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.410652] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 2.410653] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 2.410661] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 2.410662] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 2.410706] usbcore: registered new interface driver usb-storage
|
||||
[ 2.410735] mousedev: PS/2 mouse device common for all mice
|
||||
[ 2.410834] usbcore: registered new interface driver usbhid
|
||||
[ 2.410835] usbhid: USB HID core driver
|
||||
[ 2.410850] TCP: cubic registered
|
||||
[ 2.410852] NET: Registered protocol family 17
|
||||
[ 2.411039] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 2.411050] devtmpfs: mounted
|
||||
[ 2.411057] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
|
||||
INIT: version 2.88 booting
|
||||
|
||||
Starting udev
|
||||
[ 2.446370] udevd[609]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
|
||||
[ 2.521984] random: dd urandom read with 17 bits of entropy available
|
||||
Populating dev cache
|
||||
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
Mon Jan 27 08:00:00 UTC 2014
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
|
||||
INIT: Entering runlevel: 5
|
||||
|
||||
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,11 +0,0 @@
|
||||
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
@@ -1,18 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:53:59
|
||||
gem5 executing on e108600-lin, pid 23916
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 51111167192000 because m5_exit instruction encountered
|
||||
@@ -1,878 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 51.071102 # Number of seconds simulated
|
||||
sim_ticks 51071102402000 # Number of ticks simulated
|
||||
final_tick 51071102402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1747137 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2084338 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 95484785421 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 679432 # Number of bytes of host memory used
|
||||
host_seconds 534.86 # Real time elapsed on the host
|
||||
sim_insts 934475925 # Number of instructions simulated
|
||||
sim_ops 1114831373 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.dtb.walker 487168 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 439168 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 5588020 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 87025992 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::realview.ide 439360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 93979708 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 5588020 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5588020 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 115462912 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 115483492 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 7612 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 6862 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 91720 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1359794 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 6865 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1472853 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1804108 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1806681 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 9539 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 8599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 109416 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1704016 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 8603 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1840174 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 109416 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 109416 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2260827 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2261230 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2260827 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 9539 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 8599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 109416 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1704419 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 8603 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4101404 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 297729 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walksLong 297729 # Table walker walks initiated with long descriptors
|
||||
system.cpu.dtb.walker.walkWaitTime::samples 297729 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::0 297729 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::total 297729 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walkPageSizes::4K 228847 88.79% 88.79% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::2M 28897 11.21% 100.00% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::total 257744 # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 297729 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 297729 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 257744 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 257744 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 555473 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 192113611 # DTB read hits
|
||||
system.cpu.dtb.read_misses 218086 # DTB read misses
|
||||
system.cpu.dtb.write_hits 176013555 # DTB write hits
|
||||
system.cpu.dtb.write_misses 79643 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 85167 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 10256 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 22356 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 192331697 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 176093198 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 368127166 # DTB hits
|
||||
system.cpu.dtb.misses 297729 # DTB misses
|
||||
system.cpu.dtb.accesses 368424895 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 128928 # Table walker walks requested
|
||||
system.cpu.itb.walker.walksLong 128928 # Table walker walks initiated with long descriptors
|
||||
system.cpu.itb.walker.walkWaitTime::samples 128928 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.itb.walker.walkWaitTime::0 128928 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.itb.walker.walkWaitTime::total 128928 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution
|
||||
system.cpu.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution
|
||||
system.cpu.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution
|
||||
system.cpu.itb.walker.walkPageSizes::4K 115252 99.04% 99.04% # Table walker page sizes translated
|
||||
system.cpu.itb.walker.walkPageSizes::2M 1122 0.96% 100.00% # Table walker page sizes translated
|
||||
system.cpu.itb.walker.walkPageSizes::total 116374 # Table walker page sizes translated
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 128928 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 128928 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 116374 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 116374 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 245302 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 935011975 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 128928 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 59711 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 935140903 # ITB inst accesses
|
||||
system.cpu.itb.hits 935011975 # DTB hits
|
||||
system.cpu.itb.misses 128928 # DTB misses
|
||||
system.cpu.itb.accesses 935140903 # DTB accesses
|
||||
system.cpu.numPwrStateTransitions 33906 # Number of power state transitions
|
||||
system.cpu.pwrStateClkGateDist::samples 16953 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 2979611399.652038 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 59761128093.250465 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::underflows 7631 45.01% 45.01% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.78% 99.79% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::max_value 1988782908468 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::total 16953 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateResidencyTicks::ON 557750343699 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 50513352058301 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 102142221758 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 16953 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 934475925 # Number of instructions committed
|
||||
system.cpu.committedOps 1114831373 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1036744712 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 878021 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 59056085 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 135851428 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1036744712 # number of integer instructions
|
||||
system.cpu.num_fp_insts 878021 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1380118426 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 809399347 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 1413239 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 747664 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 207723168 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 207152857 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 368379179 # number of memory refs
|
||||
system.cpu.num_load_insts 192305014 # Number of load instructions
|
||||
system.cpu.num_store_insts 176074165 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 101026720885.444443 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1115500872.555553 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.010921 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.989079 # Percentage of idle cycles
|
||||
system.cpu.Branches 206489174 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 744480688 66.74% 66.74% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2418794 0.22% 66.96% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 103036 0.01% 66.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 8 0.00% 66.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 13 0.00% 66.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 21 0.00% 66.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 66.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 66.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 66.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMisc 106782 0.01% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.98% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 192192210 17.23% 84.21% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 175415772 15.73% 99.93% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMemRead 112804 0.01% 99.94% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMemWrite 658393 0.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1115488522 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 12292096 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999911 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 356005277 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 12292608 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 28.960923 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 13850500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999911 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 1.000000 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 1.000000 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1485484203 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1485484203 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 178905891 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 178905891 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 166844782 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 166844782 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 437201 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 437201 # number of SoftPFReq hits
|
||||
system.cpu.dcache.WriteLineReq_hits::cpu.data 338801 # number of WriteLineReq hits
|
||||
system.cpu.dcache.WriteLineReq_hits::total 338801 # number of WriteLineReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4589501 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 4589501 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 4852460 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 4852460 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 346089474 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 346089474 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 346526675 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 346526675 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 6353340 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 6353340 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2735988 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2735988 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1721890 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1721890 # number of SoftPFReq misses
|
||||
system.cpu.dcache.WriteLineReq_misses::cpu.data 1253245 # number of WriteLineReq misses
|
||||
system.cpu.dcache.WriteLineReq_misses::total 1253245 # number of WriteLineReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 264796 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 264796 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 10342573 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 10342573 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 12064463 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 12064463 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 185259231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 185259231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 169580770 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 169580770 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2159091 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 2159091 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1592046 # number of WriteLineReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteLineReq_accesses::total 1592046 # number of WriteLineReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4854297 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 4854297 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4852461 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 4852461 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 356432047 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 356432047 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 358591138 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 358591138 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034294 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.034294 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.016134 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.016134 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.797507 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.797507 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787191 # miss rate for WriteLineReq accesses
|
||||
system.cpu.dcache.WriteLineReq_miss_rate::total 0.787191 # miss rate for WriteLineReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.054549 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.054549 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.029017 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.033644 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.033644 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 9441403 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 9441403 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 14554443 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.984790 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 920573389 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 14554955 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 63.248110 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 6040365000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.984790 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 949683309 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 949683309 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 920573389 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 920573389 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 920573389 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 920573389 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 920573389 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 920573389 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 14554960 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 14554960 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 14554960 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 14554960 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 14554960 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 14554960 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 935128349 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 935128349 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 935128349 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 935128349 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 935128349 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 935128349 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015565 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.015565 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.015565 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.015565 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.015565 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.015565 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 14554443 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 14554443 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1939529 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65410.509732 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 51207751 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2002275 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.574784 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 373950000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9607.000136 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 373.212421 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 441.072045 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6073.861347 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48915.363784 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.146591 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005695 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006730 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092680 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.746389 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998085 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 323 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 62423 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 323 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1416 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5058 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55500 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004929 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952499 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 439130926 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 439130926 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 564464 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 243894 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 808358 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 9441403 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 9441403 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 14552867 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 14552867 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 32762 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 32762 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1717134 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1717134 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14467928 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 14467928 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7961263 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 7961263 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::cpu.data 682418 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::total 682418 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 564464 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 243894 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14467928 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 9678397 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 24954683 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 564464 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 243894 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14467928 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 9678397 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 24954683 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7612 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6862 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 14474 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 982214 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 982214 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 87032 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 87032 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 378763 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 378763 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::cpu.data 570827 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::total 570827 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7612 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 6862 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 87032 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1360977 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1462483 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7612 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 6862 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 87032 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1360977 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1462483 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 572076 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 250756 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 822832 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 9441403 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 9441403 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 14552867 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 14552867 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 36640 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 36640 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2699348 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 2699348 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14554960 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 14554960 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 8340026 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 8340026 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1253245 # number of InvalidateReq accesses(hits+misses)
|
||||
system.cpu.l2cache.InvalidateReq_accesses::total 1253245 # number of InvalidateReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 572076 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 250756 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 14554960 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 11039374 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 26417166 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 572076 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 250756 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 14554960 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 11039374 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 26417166 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013306 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.027365 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.017590 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.105841 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.105841 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.363871 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.363871 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005980 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005980 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045415 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045415 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.455479 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.455479 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013306 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.027365 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005980 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.123284 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.055361 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013306 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.027365 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005980 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.123284 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.055361 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1697477 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1697477 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 54350593 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 27503016 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1759 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1286731 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 24181717 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 33519 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 33519 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 9441403 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 14554443 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2850693 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 36640 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 36641 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2699348 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2699348 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 14554960 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 8340026 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::InvalidateReq 1253245 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::InvalidateResp 1253245 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43673813 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37084586 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 770772 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1726308 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 83255479 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1863020692 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1310959042 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3083088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6905232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 3183968054 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1977015 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 108689536 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 57027218 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.010978 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.104200 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 56401167 98.90% 98.90% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 626051 1.10% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 57027218 # Request fanout histogram
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.iobus.trans_dist::ReadReq 40168 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 40168 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 136429 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 136429 # Transaction distribution
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47254 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::total 122136 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230978 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.realview.ide.dma::total 230978 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 353194 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47274 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::total 155266 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ide.dma::total 7334344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 7491696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.replacements 115471 # number of replacements
|
||||
system.iocache.tags.tagsinuse 10.402763 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 13082091783509 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ethernet 3.557357 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_blocks::realview.ide 6.845405 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ethernet 0.222335 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::realview.ide 0.427838 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.650173 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 1039758 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 1039758 # Number of data accesses
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::realview.ide 8825 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 8862 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115489 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115529 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115489 # number of overall misses
|
||||
system.iocache.overall_misses::total 115529 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8825 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8862 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115489 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115529 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115489 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115529 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
||||
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
||||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.membus.snoop_filter.tot_requests 4206457 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 2089632 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 3012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 38191 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 527322 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33519 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 33519 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1804108 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 249631 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4439 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4440 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 981656 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 981656 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 489131 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 677491 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 677491 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122136 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6648 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6027224 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6156066 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346529 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 346529 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6502595 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155266 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202241248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 202409942 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391552 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 7391552 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 209801494 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 4278167 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.008735 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.093051 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 4240798 99.13% 99.13% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 37369 0.87% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4278167 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
||||
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
||||
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
|
||||
system.realview.ethernet.totPackets 3 # Total Packets
|
||||
system.realview.ethernet.totBytes 966 # Total Bytes
|
||||
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
||||
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
|
||||
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
||||
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
||||
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
||||
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
||||
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
||||
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
||||
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
||||
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
||||
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
||||
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
||||
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
|
||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
||||
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
||||
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
||||
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,183 +0,0 @@
|
||||
[ 0.000000] Initializing cgroup subsys cpu
|
||||
[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
|
||||
[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
|
||||
[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
|
||||
[ 0.000000] Memory limited to 256MB
|
||||
[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
|
||||
[ 0.000000] On node 0 totalpages: 65536
|
||||
[ 0.000000] DMA zone: 896 pages used for memmap
|
||||
[ 0.000000] DMA zone: 0 pages reserved
|
||||
[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
|
||||
[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
|
||||
[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
|
||||
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
|
||||
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
|
||||
[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
|
||||
[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
|
||||
[ 0.000000] Virtual kernel memory layout:
|
||||
[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
|
||||
[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
|
||||
[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
|
||||
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
|
||||
[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
|
||||
[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
|
||||
[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
|
||||
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
[ 0.000000] Preemptible hierarchical RCU implementation.
|
||||
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
|
||||
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000013] Console: colour dummy device 80x25
|
||||
[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000015] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000066] hw perfevents: no hardware support available
|
||||
[ 1.060049] CPU1: failed to come online
|
||||
[ 2.080098] CPU2: failed to come online
|
||||
[ 3.100148] CPU3: failed to come online
|
||||
[ 3.100150] Brought up 1 CPUs
|
||||
[ 3.100151] SMP: Total of 1 processors activated.
|
||||
[ 3.100177] devtmpfs: initialized
|
||||
[ 3.100579] atomic64_test: passed
|
||||
[ 3.100603] regulator-dummy: no parameters
|
||||
[ 3.100844] NET: Registered protocol family 16
|
||||
[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.100981] Serial: AMBA PL011 UART driver
|
||||
[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.101160] console [ttyAMA0] enabled
|
||||
[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130356] 3V3: 3300 mV
|
||||
[ 3.130377] vgaarb: loaded
|
||||
[ 3.130406] SCSI subsystem initialized
|
||||
[ 3.130425] libata version 3.00 loaded.
|
||||
[ 3.130450] usbcore: registered new interface driver usbfs
|
||||
[ 3.130457] usbcore: registered new interface driver hub
|
||||
[ 3.130471] usbcore: registered new device driver usb
|
||||
[ 3.130482] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.130487] PTP clock support registered
|
||||
[ 3.130559] Switched to clocksource arch_sys_counter
|
||||
[ 3.131204] NET: Registered protocol family 2
|
||||
[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.131263] TCP: reno registered
|
||||
[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.131281] NET: Registered protocol family 1
|
||||
[ 3.131311] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.131311] RPC: Registered udp transport module.
|
||||
[ 3.131312] RPC: Registered tcp transport module.
|
||||
[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.131315] PCI: CLS 0 bytes, default 64
|
||||
[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.132687] fuse init (API version 7.23)
|
||||
[ 3.132738] msgmni has been set to 469
|
||||
[ 3.133992] io scheduler noop registered
|
||||
[ 3.134025] io scheduler cfq registered (default)
|
||||
[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.134302] pci_bus 0000:00: scanning bus
|
||||
[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.134330] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.134337] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.134354] pci_bus 0000:00: fixups for bus
|
||||
[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.134362] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.134366] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.134373] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.134378] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.134813] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.135009] scsi0 : ata_piix
|
||||
[ 3.135063] scsi1 : ata_piix
|
||||
[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.135150] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.290572] ata1.00: configured for UDMA/33
|
||||
[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.290733] sda: sda1
|
||||
[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.410886] usbcore: registered new interface driver usb-storage
|
||||
[ 3.410912] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.411009] usbcore: registered new interface driver usbhid
|
||||
[ 3.411010] usbhid: USB HID core driver
|
||||
[ 3.411025] TCP: cubic registered
|
||||
[ 3.411026] NET: Registered protocol family 17
|
||||
[ 3.411204] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.411214] devtmpfs: mounted
|
||||
[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
|
||||
INIT: version 2.88 booting
|
||||
|
||||
Starting udev
|
||||
[ 3.446950] udevd[607]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
|
||||
[ 3.532262] random: dd urandom read with 19 bits of entropy available
|
||||
Populating dev cache
|
||||
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
Mon Jan 27 08:00:00 UTC 2014
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
|
||||
INIT: Entering runlevel: 5
|
||||
|
||||
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,13 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
@@ -1,18 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 11 2016 00:00:58
|
||||
gem5 started Oct 13 2016 20:42:59
|
||||
gem5 executing on e108600-lin, pid 17314
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 47405012960500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,183 +0,0 @@
|
||||
[ 0.000000] Initializing cgroup subsys cpu
|
||||
[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
|
||||
[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
|
||||
[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
|
||||
[ 0.000000] Memory limited to 256MB
|
||||
[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
|
||||
[ 0.000000] On node 0 totalpages: 65536
|
||||
[ 0.000000] DMA zone: 896 pages used for memmap
|
||||
[ 0.000000] DMA zone: 0 pages reserved
|
||||
[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
|
||||
[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
|
||||
[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
|
||||
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
|
||||
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
|
||||
[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
|
||||
[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
|
||||
[ 0.000000] Virtual kernel memory layout:
|
||||
[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
|
||||
[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
|
||||
[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
|
||||
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
|
||||
[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
|
||||
[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
|
||||
[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
|
||||
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
[ 0.000000] Preemptible hierarchical RCU implementation.
|
||||
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
|
||||
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000029] Console: colour dummy device 80x25
|
||||
[ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000033] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000047] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000190] hw perfevents: no hardware support available
|
||||
[ 0.060052] CPU1: Booted secondary processor
|
||||
[ 1.080092] CPU2: failed to come online
|
||||
[ 2.100178] CPU3: failed to come online
|
||||
[ 2.100181] Brought up 2 CPUs
|
||||
[ 2.100182] SMP: Total of 2 processors activated.
|
||||
[ 2.100254] devtmpfs: initialized
|
||||
[ 2.100899] atomic64_test: passed
|
||||
[ 2.100953] regulator-dummy: no parameters
|
||||
[ 2.101395] NET: Registered protocol family 16
|
||||
[ 2.101565] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 2.101572] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 2.102371] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 2.102374] Serial: AMBA PL011 UART driver
|
||||
[ 2.102603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 2.102648] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 2.103226] console [ttyAMA0] enabled
|
||||
[ 2.103397] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 2.103474] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 2.103550] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 2.103618] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 2.130484] 3V3: 3300 mV
|
||||
[ 2.130542] vgaarb: loaded
|
||||
[ 2.130598] SCSI subsystem initialized
|
||||
[ 2.130640] libata version 3.00 loaded.
|
||||
[ 2.130696] usbcore: registered new interface driver usbfs
|
||||
[ 2.130716] usbcore: registered new interface driver hub
|
||||
[ 2.130745] usbcore: registered new device driver usb
|
||||
[ 2.130775] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 2.130785] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 2.130805] PTP clock support registered
|
||||
[ 2.130963] Switched to clocksource arch_sys_counter
|
||||
[ 2.132610] NET: Registered protocol family 2
|
||||
[ 2.132708] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 2.132728] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 2.132748] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 2.132775] TCP: reno registered
|
||||
[ 2.132782] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.132796] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.132838] NET: Registered protocol family 1
|
||||
[ 2.132904] RPC: Registered named UNIX socket transport module.
|
||||
[ 2.132915] RPC: Registered udp transport module.
|
||||
[ 2.132923] RPC: Registered tcp transport module.
|
||||
[ 2.132932] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 2.132945] PCI: CLS 0 bytes, default 64
|
||||
[ 2.133141] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 2.133256] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 2.135328] fuse init (API version 7.23)
|
||||
[ 2.135440] msgmni has been set to 469
|
||||
[ 2.135797] io scheduler noop registered
|
||||
[ 2.135862] io scheduler cfq registered (default)
|
||||
[ 2.136433] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.136447] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.136458] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.136472] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.136482] pci_bus 0000:00: scanning bus
|
||||
[ 2.136494] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.136508] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 2.136523] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.136564] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 2.136577] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.136588] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.136600] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.136611] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.136622] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.136634] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.136675] pci_bus 0000:00: fixups for bus
|
||||
[ 2.136684] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 2.136697] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 2.136718] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 2.136727] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 2.136739] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 2.136748] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 2.136760] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 2.136773] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 2.136787] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 2.136801] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 2.136813] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 2.136825] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 2.136837] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 2.136849] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 2.137426] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 2.137740] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 2.137750] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 2.137778] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 2.138110] scsi0 : ata_piix
|
||||
[ 2.138200] scsi1 : ata_piix
|
||||
[ 2.138235] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 2.138247] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 2.138381] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 2.138393] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.138410] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.138423] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.290984] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.290994] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.291024] ata1.00: configured for UDMA/33
|
||||
[ 2.291083] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.291212] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.291226] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.291255] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.291265] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.291288] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.291434] sda: sda1
|
||||
[ 2.291570] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.411274] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.411288] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.411313] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 2.411324] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 2.411348] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 2.411360] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 2.411448] usbcore: registered new interface driver usb-storage
|
||||
[ 2.411534] mousedev: PS/2 mouse device common for all mice
|
||||
[ 2.411744] usbcore: registered new interface driver usbhid
|
||||
[ 2.411754] usbhid: USB HID core driver
|
||||
[ 2.411794] TCP: cubic registered
|
||||
[ 2.411802] NET: Registered protocol family 17
|
||||
[ 2.412301] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 2.412341] devtmpfs: mounted
|
||||
[ 2.412395] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
|
||||
INIT: version 2.88 booting
|
||||
|
||||
Starting udev
|
||||
[ 2.452586] udevd[609]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
|
||||
[ 2.534161] random: dd urandom read with 18 bits of entropy available
|
||||
Populating dev cache
|
||||
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
Mon Jan 27 08:00:00 UTC 2014
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
|
||||
INIT: Entering runlevel: 5
|
||||
|
||||
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,12 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
|
||||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
@@ -1,18 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 11 2016 00:00:58
|
||||
gem5 started Oct 13 2016 20:50:54
|
||||
gem5 executing on e108600-lin, pid 17458
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 51821888787500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,183 +0,0 @@
|
||||
[ 0.000000] Initializing cgroup subsys cpu
|
||||
[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
|
||||
[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
|
||||
[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
|
||||
[ 0.000000] Memory limited to 256MB
|
||||
[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
|
||||
[ 0.000000] On node 0 totalpages: 65536
|
||||
[ 0.000000] DMA zone: 896 pages used for memmap
|
||||
[ 0.000000] DMA zone: 0 pages reserved
|
||||
[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
|
||||
[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
|
||||
[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
|
||||
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
|
||||
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
|
||||
[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
|
||||
[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
|
||||
[ 0.000000] Virtual kernel memory layout:
|
||||
[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
|
||||
[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
|
||||
[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
|
||||
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
|
||||
[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
|
||||
[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
|
||||
[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
|
||||
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
[ 0.000000] Preemptible hierarchical RCU implementation.
|
||||
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
|
||||
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000040] Console: colour dummy device 80x25
|
||||
[ 0.000043] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000046] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000066] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000069] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000252] hw perfevents: no hardware support available
|
||||
[ 1.060135] CPU1: failed to come online
|
||||
[ 2.080266] CPU2: failed to come online
|
||||
[ 3.100397] CPU3: failed to come online
|
||||
[ 3.100402] Brought up 1 CPUs
|
||||
[ 3.100404] SMP: Total of 1 processors activated.
|
||||
[ 3.100503] devtmpfs: initialized
|
||||
[ 3.101571] atomic64_test: passed
|
||||
[ 3.101646] regulator-dummy: no parameters
|
||||
[ 3.102401] NET: Registered protocol family 16
|
||||
[ 3.102664] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.102675] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.103283] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.103290] Serial: AMBA PL011 UART driver
|
||||
[ 3.103646] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.103712] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.104302] console [ttyAMA0] enabled
|
||||
[ 3.104405] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.104456] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.104507] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.104554] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.131002] 3V3: 3300 mV
|
||||
[ 3.131076] vgaarb: loaded
|
||||
[ 3.131168] SCSI subsystem initialized
|
||||
[ 3.131239] libata version 3.00 loaded.
|
||||
[ 3.131320] usbcore: registered new interface driver usbfs
|
||||
[ 3.131346] usbcore: registered new interface driver hub
|
||||
[ 3.131401] usbcore: registered new device driver usb
|
||||
[ 3.131444] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.131455] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.131477] PTP clock support registered
|
||||
[ 3.131699] Switched to clocksource arch_sys_counter
|
||||
[ 3.133732] NET: Registered protocol family 2
|
||||
[ 3.133887] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.133915] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.133949] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.133976] TCP: reno registered
|
||||
[ 3.133984] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.134003] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.134067] NET: Registered protocol family 1
|
||||
[ 3.134134] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.134145] RPC: Registered udp transport module.
|
||||
[ 3.134154] RPC: Registered tcp transport module.
|
||||
[ 3.134163] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.134177] PCI: CLS 0 bytes, default 64
|
||||
[ 3.134494] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.134701] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.138130] fuse init (API version 7.23)
|
||||
[ 3.138291] msgmni has been set to 469
|
||||
[ 3.142786] io scheduler noop registered
|
||||
[ 3.142885] io scheduler cfq registered (default)
|
||||
[ 3.143673] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.143688] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.143701] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.143715] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.143727] pci_bus 0000:00: scanning bus
|
||||
[ 3.143740] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.143755] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.143773] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.143833] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.143848] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.143860] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.143873] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.143886] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.143899] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.143912] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.143970] pci_bus 0000:00: fixups for bus
|
||||
[ 3.143980] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.143994] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.144020] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.144030] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.144044] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.144054] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.144070] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.144084] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.144099] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.144114] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.144127] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.144141] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.144154] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.144168] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.145036] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.145534] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.145546] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.145577] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.146149] scsi0 : ata_piix
|
||||
[ 3.146327] scsi1 : ata_piix
|
||||
[ 3.146380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.146394] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.146583] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.146596] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.146618] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.146632] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.301733] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.301744] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.301779] ata1.00: configured for UDMA/33
|
||||
[ 3.301852] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.302048] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.302084] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.302142] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.302153] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.302182] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.302382] sda: sda1
|
||||
[ 3.302584] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.422057] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.422072] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.422102] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.422113] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.422144] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.422157] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.422289] usbcore: registered new interface driver usb-storage
|
||||
[ 3.422380] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.422670] usbcore: registered new interface driver usbhid
|
||||
[ 3.422681] usbhid: USB HID core driver
|
||||
[ 3.422731] TCP: cubic registered
|
||||
[ 3.422741] NET: Registered protocol family 17
|
||||
[ 3.423331] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.423377] devtmpfs: mounted
|
||||
[ 3.423427] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
|
||||
INIT: version 2.88 booting
|
||||
|
||||
Starting udev
|
||||
[ 3.470296] udevd[607]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
|
||||
[ 3.606651] random: dd urandom read with 20 bits of entropy available
|
||||
Populating dev cache
|
||||
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
Mon Jan 27 08:00:00 UTC 2014
|
||||
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
|
||||
|
||||
INIT: Entering runlevel: 5
|
||||
|
||||
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,11 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
@@ -1,13 +0,0 @@
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 15:10:31
|
||||
gem5 started Dec 4 2015 15:13:28
|
||||
gem5 executing on e104799-lin, pid 29885
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5144274809000 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,141 +0,0 @@
|
||||
Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
|
||||
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)
|
||||
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
|
||||
end_pfn_map = 1048576
|
||||
kernel direct mapping tables up to 100000000 @ 8000-d000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 0 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[2] active PFN ranges
|
||||
0: 0 -> 159
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
Processor #0 (Bootup-CPU)
|
||||
I/O APIC #1 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 1
|
||||
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
|
||||
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
|
||||
Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)
|
||||
Built 1 zonelists. Total pages: 30610
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 2000.001 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
using mwait in idle threads.
|
||||
CPU: Fake M5 x86_64 CPU stepping 01
|
||||
ACPI: Core revision 20070126
|
||||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812523
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
ACPI: Interpreter disabled.
|
||||
Linux Plug and Play Support v0.97 (c) Adam Belay
|
||||
pnp: PnP ACPI: disabled
|
||||
SCSI subsystem initialized
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
Time: tsc clocksource has been installed.
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
|
||||
TCP: Hash tables configured (established 4096 bind 4096)
|
||||
TCP reno registered
|
||||
Total HugeTLB memory allocated, 0
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
io scheduler noop registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
Real Time Clock Driver v1.12ac
|
||||
Linux agpgart interface v0.102 (c) Dave Jones
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
|
||||
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
floppy0: no floppy controllers found
|
||||
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
|
||||
loop: module loaded
|
||||
Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
|
||||
Copyright (c) 1999-2006 Intel Corporation.
|
||||
e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
|
||||
e100: Copyright(c) 1999-2006 Intel Corporation
|
||||
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
netconsole: not configured, aborting
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
|
||||
PIIX4: IDE controller at PCI slot 0000:00:04.0
|
||||
PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
|
||||
PIIX4: chipset revision 0
|
||||
PIIX4: not 100% native mode: will probe irqs later
|
||||
ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
|
||||
ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
|
||||
hda: M5 IDE Disk, ATA DISK drive
|
||||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
|
||||
hda: max request size: 128KiB
|
||||
hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
|
||||
hdb: unknown partition table
|
||||
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
|
||||
megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
|
||||
megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
|
||||
Fusion MPT base driver 3.04.04
|
||||
Copyright (c) 1999-2007 LSI Logic Corporation
|
||||
Fusion MPT SPI Host driver 3.04.04
|
||||
Fusion MPT SAS Host driver 3.04.04
|
||||
ieee1394: raw1394: /dev/raw1394 device initialized
|
||||
USB Universal Host Controller Interface driver v3.0
|
||||
usbcore: registered new interface driver usblp
|
||||
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
|
||||
Initializing USB Mass Storage driver...
|
||||
usbcore: registered new interface driver usb-storage
|
||||
USB Mass Storage support registered.
|
||||
PNP: No PS/2 controller found. Probing ports directly.
|
||||
serio: i8042 KBD port at 0x60,0x64 irq 1
|
||||
serio: i8042 AUX port at 0x60,0x64 irq 12
|
||||
mice: PS/2 mouse device common for all mice
|
||||
input: AT Translated Set 2 keyboard as /class/input/input0
|
||||
device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
usbcore: registered new interface driver usbhid
|
||||
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
|
||||
oprofile: using timer interrupt.
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 232k freed
|
||||
|
||||
INIT: version 2.86 booting
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,13 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: Reading current count from inactive timer.
|
||||
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
warn: x86 cpuid: unknown family 0x8086
|
||||
hack: Assuming logical destinations are 1 << id.
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
warn: Unknown mouse command 0xe1.
|
||||
@@ -1,15 +0,0 @@
|
||||
Redirecting stdout to build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
|
||||
Redirecting stderr to build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 15 2016 21:26:21
|
||||
gem5 started Mar 15 2016 21:35:42
|
||||
gem5 executing on phenom, pid 15979
|
||||
command line: build/X86_MESI_Two_Level/gem5.opt -d build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5220166723500 because m5_exit instruction encountered
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,142 +0,0 @@
|
||||
Linux version 2.6.22.9 (gblack@fajita) (gcc version 4.1.2 (Gentoo 4.1.2 p1.1)) #12 SMP Fri Feb 27 22:10:33 PST 2009
|
||||
Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
BIOS-provided physical RAM map:
|
||||
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
|
||||
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
|
||||
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
|
||||
BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)
|
||||
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
|
||||
end_pfn_map = 1048576
|
||||
kernel direct mapping tables up to 100000000 @ 8000-d000
|
||||
DMI 2.5 present.
|
||||
Zone PFN ranges:
|
||||
DMA 0 -> 4096
|
||||
DMA32 4096 -> 1048576
|
||||
Normal 1048576 -> 1048576
|
||||
early_node_map[2] active PFN ranges
|
||||
0: 0 -> 159
|
||||
0: 256 -> 32768
|
||||
Intel MultiProcessor Specification v1.4
|
||||
MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
|
||||
Processor #0 (Bootup-CPU)
|
||||
Processor #1
|
||||
I/O APIC #2 at 0xFEC00000.
|
||||
Setting APIC routing to flat
|
||||
Processors: 2
|
||||
Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)
|
||||
PERCPU: Allocating 34160 bytes of per cpu data
|
||||
Built 1 zonelists. Total pages: 30613
|
||||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
Marking TSC unstable due to TSCs unsynchronized
|
||||
time.c: Detected 2000.000 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
Checking aperture...
|
||||
Memory: 121996k/131072k available (3699k kernel code, 8524k reserved, 1767k data, 248k init)
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
Mount-cache hash table entries: 256
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
using mwait in idle threads.
|
||||
Freeing SMP alternatives: 34k freed
|
||||
Using local APIC timer interrupts.
|
||||
result 7812506
|
||||
Detected 7.812 MHz APIC timer.
|
||||
Booting processor 1/2 APIC 0x1
|
||||
Initializing CPU#1
|
||||
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
|
||||
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
||||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
Fake M5 x86_64 CPU stepping 01
|
||||
Brought up 2 CPUs
|
||||
migration_cost=11
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
SCSI subsystem initialized
|
||||
usbcore: registered new interface driver usbfs
|
||||
usbcore: registered new interface driver hub
|
||||
usbcore: registered new device driver usb
|
||||
PCI: Probing PCI hardware
|
||||
PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16
|
||||
PCI-GART: No AMD northbridge found.
|
||||
NET: Registered protocol family 2
|
||||
IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 4096 (order: 4, 98304 bytes)
|
||||
TCP bind hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
TCP: Hash tables configured (established 4096 bind 4096)
|
||||
TCP reno registered
|
||||
Total HugeTLB memory allocated, 0
|
||||
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
|
||||
io scheduler noop registered
|
||||
io scheduler deadline registered
|
||||
io scheduler cfq registered (default)
|
||||
Real Time Clock Driver v1.12ac
|
||||
Linux agpgart interface v0.102 (c) Dave Jones
|
||||
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
|
||||
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
|
||||
floppy0: no floppy controllers found
|
||||
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
|
||||
loop: module loaded
|
||||
Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
|
||||
Copyright (c) 1999-2006 Intel Corporation.
|
||||
e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
|
||||
e100: Copyright(c) 1999-2006 Intel Corporation
|
||||
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
|
||||
netconsole: not configured, aborting
|
||||
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
|
||||
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
|
||||
PIIX4: IDE controller at PCI slot 0000:00:04.0
|
||||
PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
|
||||
PIIX4: chipset revision 0
|
||||
PIIX4: not 100% native mode: will probe irqs later
|
||||
ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
|
||||
ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
|
||||
hda: M5 IDE Disk, ATA DISK drive
|
||||
hdb: M5 IDE Disk, ATA DISK drive
|
||||
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
|
||||
hda: max request size: 128KiB
|
||||
hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
|
||||
hda: hda1
|
||||
hdb: max request size: 128KiB
|
||||
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
|
||||
hdb: unknown partition table
|
||||
megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
|
||||
megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
|
||||
megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
|
||||
Fusion MPT base driver 3.04.04
|
||||
Copyright (c) 1999-2007 LSI Logic Corporation
|
||||
Fusion MPT SPI Host driver 3.04.04
|
||||
Fusion MPT SAS Host driver 3.04.04
|
||||
ieee1394: raw1394: /dev/raw1394 device initialized
|
||||
USB Universal Host Controller Interface driver v3.0
|
||||
usbcore: registered new interface driver usblp
|
||||
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
|
||||
Initializing USB Mass Storage driver...
|
||||
usbcore: registered new interface driver usb-storage
|
||||
USB Mass Storage support registered.
|
||||
serio: i8042 KBD port at 0x60,0x64 irq 1
|
||||
serio: i8042 AUX port at 0x60,0x64 irq 12
|
||||
mice: PS/2 mouse device common for all mice
|
||||
input: AT Translated Set 2 keyboard as /class/input/input0
|
||||
device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
|
||||
usbcore: registered new interface driver usbhid
|
||||
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
|
||||
oprofile: using timer interrupt.
|
||||
TCP cubic registered
|
||||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 248k freed
|
||||
|
||||
INIT: version 2.86 booting
|
||||
|
||||
@@ -1,27 +0,0 @@
|
||||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
root.system.readfile = os.path.join(tests_root, 'halt.sh')
|
||||
@@ -1,752 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=true
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=200000000
|
||||
time_sync_spin_threshold=200000
|
||||
|
||||
[system]
|
||||
type=SparcSystem
|
||||
children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
hypervisor_addr=1099243257856
|
||||
hypervisor_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin
|
||||
hypervisor_desc=system.hypervisor_desc
|
||||
hypervisor_desc_addr=133446500352
|
||||
hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=atomic
|
||||
mem_ranges=1048576:68157439:0:0:0:0 2147483648:2415919103:0:0:0:0
|
||||
memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
nvram=system.nvram
|
||||
nvram_addr=133429198848
|
||||
nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1
|
||||
openboot_addr=1099243716608
|
||||
openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
partition_desc=system.partition_desc
|
||||
partition_desc_addr=133445976064
|
||||
partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin
|
||||
power_model=Null
|
||||
readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
|
||||
reset_addr=1099243192320
|
||||
reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin
|
||||
rom=system.rom
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=100
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
power_model=Null
|
||||
ranges=133412421632:133412421639:0:0:0:0 134217728000:554050781183:0:0:0:0 644245094400:652835028991:0:0:0:0 725849473024:1095485095935:0:0:0:0 1099255955456:1099255955463:0:0:0:0
|
||||
req_size=16
|
||||
resp_size=16
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[2]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=2
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb interrupts isa itb tracer
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=SparcISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
eventq_index=0
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=2
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.disk0]
|
||||
type=MmDisk
|
||||
children=image
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
image=system.disk0.image
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=134217728000
|
||||
pio_latency=200
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
children=child
|
||||
child=system.disk0.image.child
|
||||
eventq_index=0
|
||||
image_file=
|
||||
read_only=false
|
||||
table_size=65536
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2
|
||||
read_only=true
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=200000
|
||||
|
||||
[system.hypervisor_desc]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
power_model=Null
|
||||
range=133446500352:133446508543:0:0:0:0
|
||||
port=system.membus.master[5]
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
eventq_index=0
|
||||
sys=system
|
||||
|
||||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
|
||||
slave=system.bridge.master
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=0
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.nvram]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
power_model=Null
|
||||
range=133429198848:133429207039:0:0:0:0
|
||||
port=system.membus.master[4]
|
||||
|
||||
[system.partition_desc]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
power_model=Null
|
||||
range=133445976064:133445984255:0:0:0:0
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.physmem0]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
power_model=Null
|
||||
range=1048576:68157439:0:0:0:0
|
||||
port=system.membus.master[7]
|
||||
|
||||
[system.physmem1]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
power_model=Null
|
||||
range=2147483648:2415919103:0:0:0:0
|
||||
port=system.membus.master[8]
|
||||
|
||||
[system.rom]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
power_model=Null
|
||||
range=1099243192320:1099251580927:0:0:0:0
|
||||
port=system.membus.master[3]
|
||||
|
||||
[system.t1000]
|
||||
type=T1000
|
||||
children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
|
||||
eventq_index=0
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_clk]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=644245094400
|
||||
pio_latency=200
|
||||
pio_size=4294967296
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.t1000.fake_jbi]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=549755813888
|
||||
pio_latency=200
|
||||
pio_size=4294967296
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.t1000.fake_l2_1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=725849473024
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.t1000.fake_l2_2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=725849473088
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.t1000.fake_l2_3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=725849473152
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.t1000.fake_l2_4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=725849473216
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.t1000.fake_l2esr_1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=734439407616
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.t1000.fake_l2esr_2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=734439407680
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.t1000.fake_l2esr_3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=734439407744
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.t1000.fake_l2esr_4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=734439407808
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.t1000.fake_membnks]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=648540061696
|
||||
pio_latency=200
|
||||
pio_size=16384
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.t1000.fake_ssi]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=1095216660480
|
||||
pio_latency=200
|
||||
pio_size=268435456
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.t1000.hterm]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.t1000.htod]
|
||||
type=DumbTOD
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=1099255906296
|
||||
pio_latency=200
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.t1000.hvuart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=1099255955456
|
||||
pio_latency=200
|
||||
platform=system.t1000
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.t1000.hterm
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.t1000.iob]
|
||||
type=Iob
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[0]
|
||||
|
||||
[system.t1000.pterm]
|
||||
type=Terminal
|
||||
eventq_index=0
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.t1000.puart0]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=133412421632
|
||||
pio_latency=200
|
||||
platform=system.t1000
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.t1000.pterm
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,40 +0,0 @@
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.145519 rounded to 0
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
@@ -1,19 +0,0 @@
|
||||
Redirecting stdout to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simout
|
||||
Redirecting stderr to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 4 2017 02:52:44
|
||||
gem5 started Apr 4 2017 02:52:54
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 16631
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
|
||||
Global frequency set at 2000000000 ticks per second
|
||||
info: No kernel set for full system simulation. Assuming you know what you're doing
|
||||
0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
|
||||
0: system.t1000.htod: Real-time clock set to 1230768000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Ignoring write to SPARC ERROR regsiter
|
||||
info: Ignoring write to SPARC ERROR regsiter
|
||||
Exiting @ tick 4467555024 because m5_exit instruction encountered
|
||||
@@ -1,291 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.233778 # Number of seconds simulated
|
||||
sim_ticks 4467555024 # Number of ticks simulated
|
||||
final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 2000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2912008 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2913153 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5838373 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 551728 # Number of bytes of host memory used
|
||||
host_seconds 765.21 # Real time elapsed on the host
|
||||
sim_insts 2228284650 # Number of instructions simulated
|
||||
sim_ops 2229160714 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 2 # Clock period in ticks
|
||||
system.hypervisor_desc.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
|
||||
system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
|
||||
system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
|
||||
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
|
||||
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
|
||||
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
|
||||
system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem0.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.physmem0.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
|
||||
system.physmem0.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
|
||||
system.physmem0.bytes_read::total 709825348 # Number of bytes read from this memory
|
||||
system.physmem0.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem0.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem0.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
|
||||
system.physmem0.bytes_written::total 15400223 # Number of bytes written to this memory
|
||||
system.physmem0.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
|
||||
system.physmem0.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
|
||||
system.physmem0.num_reads::total 165224885 # Number of read requests responded to by this memory
|
||||
system.physmem0.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem0.num_writes::total 1927067 # Number of write requests responded to by this memory
|
||||
system.physmem0.num_other::cpu.data 14 # Number of other requests responded to by this memory
|
||||
system.physmem0.num_other::total 14 # Number of other requests responded to by this memory
|
||||
system.physmem0.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem1.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
|
||||
system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
|
||||
system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory
|
||||
system.physmem1.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem1.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem1.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
|
||||
system.physmem1.bytes_written::total 897268422 # Number of bytes written to this memory
|
||||
system.physmem1.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
|
||||
system.physmem1.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
|
||||
system.physmem1.num_reads::total 2403489130 # Number of read requests responded to by this memory
|
||||
system.physmem1.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem1.num_writes::total 187387796 # Number of write requests responded to by this memory
|
||||
system.physmem1.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem1.num_other::total 5403067 # Number of other requests responded to by this memory
|
||||
system.physmem1.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem1.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem1.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem1.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
|
||||
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
|
||||
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
|
||||
system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 2 # Clock period in ticks
|
||||
system.cpu.pwrStateResidencyTicks::ON 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 2228284650 # Number of instructions committed
|
||||
system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 44037246 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1839325658 # number of integer instructions
|
||||
system.cpu.num_fp_insts 14608322 # number of float instructions
|
||||
system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 547951940 # number of memory refs
|
||||
system.cpu.num_load_insts 349807670 # Number of load instructions
|
||||
system.cpu.num_store_insts 198144270 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 441057355 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 49673656 2.22% 2.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1619015933 72.49% 74.71% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 0 0.00% 74.71% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 74.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 8419779 0.38% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.09% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 352214742 15.77% 90.86% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 198071026 8.87% 99.72% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMemRead 4059787 0.18% 99.90% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMemWrite 2128756 0.10% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2233583679 # Class of executed instruction
|
||||
system.disk0.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.iobus.trans_dist::ReadReq 4348554 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 4348554 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 7569 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 7569 # Transaction distribution
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_membnks.pio 40 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_1.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_1.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_2.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_3.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_4.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_jbi.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.puart0.pio 29218 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.t1000.hvuart.pio 36 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.disk0.pio 8682882 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::total 8712246 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_membnks.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_1.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_2.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_3.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_4.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_1.pio 16 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_2.pio 16 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_3.pio 16 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_4.pio 16 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_jbi.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.puart0.pio 14609 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.t1000.hvuart.pio 18 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.disk0.pio 34731524 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::total 34746591 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 2573267624 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2573267624 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 189322556 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 189322556 # Transaction distribution
|
||||
system.membus.trans_dist::SwapReq 5403081 # Transaction distribution
|
||||
system.membus.trans_dist::SwapResp 5403081 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.rom.port 216148 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem0.port 306145662 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem1.port 4159053420 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::total 4465415230 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.t1000.iob.pio 64 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.t1000.htod.pio 32 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.bridge.slave 8712246 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.rom.port 174098 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.nvram.port 752 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.hypervisor_desc.port 18048 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.partition_desc.port 1216 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem0.port 28158270 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem1.port 1033506566 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::total 1070571292 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5535986522 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.rom.port 432296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem0.port 612291324 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem1.port 8318106840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::total 8930830460 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.t1000.iob.pio 256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.t1000.htod.pio 128 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.bridge.slave 34746591 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.rom.port 696392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.nvram.port 376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.hypervisor_desc.port 16792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.partition_desc.port 4846 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem0.port 112934471 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem1.port 2454584131 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::total 2602983983 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 11533814443 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 2767993261 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2767993261 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2767993261 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_clk.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_jbi.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_l2_1.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_l2_2.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_l2_3.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_l2_4.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_l2esr_1.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_l2esr_2.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_l2esr_3.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_l2esr_4.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_membnks.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.fake_ssi.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.htod.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.hvuart.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.iob.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
system.t1000.puart0.pwrStateResidencyTicks::UNDEFINED 4467555024 # Cumulative time (in ticks) in various power states
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,48 +0,0 @@
|
||||
cpu
|
||||
|
||||
Sun Fire T2000, No Keyboard
|
||||
Copyright 2006 Sun Microsystems, Inc. All rights reserved.
|
||||
OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.
|
||||
[saidi obp #30]
|
||||
Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.
|
||||
|
||||
|
||||
|
||||
Boot device: /virtual-devices/disk@0 File and args: -vV
|
||||
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
|
||||
FCode UFS Reader 1.12 00/07/17 15:48:16.
|
||||
Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot
|
||||
Loading: /platform/sun4v/ufsboot
|
||||
device path '/virtual-devices@100/disk@0:a'
|
||||
The boot filesystem is logging.
|
||||
The ufs log is empty and will not be used.
|
||||
standalone = `kernel/sparcv9/unix', args = `-v'
|
||||
|Elf64 client
|
||||
Size: /-\|/-\|0x76e40+/-\|/-\|/-\|/-\0x1c872+|/-\0x3123a Bytes
|
||||
modpath: /platform/sun4v/kernel /kernel /usr/kernel
|
||||
|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-module /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000
|
||||
module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0
|
||||
module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0
|
||||
module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0
|
||||
module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300
|
||||
\
|
||||
SunOS Release 5.10 Version Generic_118822-23 64-bit
|
||||
Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved.
|
||||
Use is subject to license terms.
|
||||
|/-\|/-\|/-\|/-\|/-Ethernet address = 0:80:3:de:ad:3
|
||||
\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/mem = 262144K (0x10000000)
|
||||
avail mem = 237879296
|
||||
root nexus = Sun Fire T2000
|
||||
pseudo0 at root
|
||||
pseudo0 is /pseudo
|
||||
scsi_vhci0 at root
|
||||
scsi_vhci0 is /scsi_vhci
|
||||
virtual-device: hsimd0
|
||||
hsimd0 is /virtual-devices@100/disk@0
|
||||
root on /virtual-devices@100/disk@0:a fstype ufs
|
||||
pseudo-device: dld0
|
||||
dld0 is /pseudo/dld@0
|
||||
cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)
|
||||
iscsi0 at root
|
||||
iscsi0 is /iscsi
|
||||
Hostname: unknown
|
||||
@@ -1,27 +0,0 @@
|
||||
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
root.system.readfile = os.path.join(tests_root, 'halt.sh')
|
||||
@@ -1,997 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=MinorCPU
|
||||
children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
branchPred=system.cpu.branchPred
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
decodeCycleInput=true
|
||||
decodeInputBufferSize=3
|
||||
decodeInputWidth=2
|
||||
decodeToExecuteForwardDelay=1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableIdling=true
|
||||
eventq_index=0
|
||||
executeAllowEarlyMemoryIssue=true
|
||||
executeBranchDelay=1
|
||||
executeCommitLimit=2
|
||||
executeCycleInput=true
|
||||
executeFuncUnits=system.cpu.executeFuncUnits
|
||||
executeInputBufferSize=7
|
||||
executeInputWidth=2
|
||||
executeIssueLimit=2
|
||||
executeLSQMaxStoreBufferStoresPerCycle=2
|
||||
executeLSQRequestsQueueSize=1
|
||||
executeLSQStoreBufferSize=5
|
||||
executeLSQTransfersQueueSize=2
|
||||
executeMaxAccessesInMemory=2
|
||||
executeMemoryCommitLimit=1
|
||||
executeMemoryIssueLimit=1
|
||||
executeMemoryWidth=0
|
||||
executeSetTraceTimeOnCommit=true
|
||||
executeSetTraceTimeOnIssue=false
|
||||
fetch1FetchLimit=1
|
||||
fetch1LineSnapWidth=0
|
||||
fetch1LineWidth=0
|
||||
fetch1ToFetch2BackwardDelay=1
|
||||
fetch1ToFetch2ForwardDelay=1
|
||||
fetch2CycleInput=true
|
||||
fetch2InputBufferSize=2
|
||||
fetch2ToDecodeForwardDelay=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
system=system
|
||||
threadPolicy=RoundRobin
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.branchPred]
|
||||
type=TournamentBP
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=262144
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.executeFuncUnits]
|
||||
type=MinorFUPool
|
||||
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
|
||||
eventq_index=0
|
||||
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits0]
|
||||
type=MinorFU
|
||||
children=opClasses timings
|
||||
cantForwardFromFUIndices=
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
|
||||
opLat=3
|
||||
timings=system.cpu.executeFuncUnits.funcUnits0.timings
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
|
||||
type=MinorOpClassSet
|
||||
children=opClasses
|
||||
eventq_index=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=IntAlu
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits0.timings]
|
||||
type=MinorFUTiming
|
||||
children=opClasses
|
||||
description=Int
|
||||
eventq_index=0
|
||||
extraAssumedLat=0
|
||||
extraCommitLat=0
|
||||
extraCommitLatExpr=Null
|
||||
mask=0
|
||||
match=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
|
||||
srcRegsRelativeLats=2
|
||||
suppress=false
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
|
||||
type=MinorOpClassSet
|
||||
eventq_index=0
|
||||
opClasses=
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits1]
|
||||
type=MinorFU
|
||||
children=opClasses timings
|
||||
cantForwardFromFUIndices=
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
|
||||
opLat=3
|
||||
timings=system.cpu.executeFuncUnits.funcUnits1.timings
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
|
||||
type=MinorOpClassSet
|
||||
children=opClasses
|
||||
eventq_index=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=IntAlu
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits1.timings]
|
||||
type=MinorFUTiming
|
||||
children=opClasses
|
||||
description=Int
|
||||
eventq_index=0
|
||||
extraAssumedLat=0
|
||||
extraCommitLat=0
|
||||
extraCommitLatExpr=Null
|
||||
mask=0
|
||||
match=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
|
||||
srcRegsRelativeLats=2
|
||||
suppress=false
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
|
||||
type=MinorOpClassSet
|
||||
eventq_index=0
|
||||
opClasses=
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits2]
|
||||
type=MinorFU
|
||||
children=opClasses timings
|
||||
cantForwardFromFUIndices=
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
|
||||
opLat=3
|
||||
timings=system.cpu.executeFuncUnits.funcUnits2.timings
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
|
||||
type=MinorOpClassSet
|
||||
children=opClasses
|
||||
eventq_index=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=IntMult
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits2.timings]
|
||||
type=MinorFUTiming
|
||||
children=opClasses
|
||||
description=Mul
|
||||
eventq_index=0
|
||||
extraAssumedLat=0
|
||||
extraCommitLat=0
|
||||
extraCommitLatExpr=Null
|
||||
mask=0
|
||||
match=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
|
||||
srcRegsRelativeLats=0
|
||||
suppress=false
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
|
||||
type=MinorOpClassSet
|
||||
eventq_index=0
|
||||
opClasses=
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits3]
|
||||
type=MinorFU
|
||||
children=opClasses
|
||||
cantForwardFromFUIndices=
|
||||
eventq_index=0
|
||||
issueLat=9
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
|
||||
opLat=9
|
||||
timings=
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
|
||||
type=MinorOpClassSet
|
||||
children=opClasses
|
||||
eventq_index=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=IntDiv
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4]
|
||||
type=MinorFU
|
||||
children=opClasses timings
|
||||
cantForwardFromFUIndices=
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
|
||||
opLat=6
|
||||
timings=system.cpu.executeFuncUnits.funcUnits4.timings
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
|
||||
type=MinorOpClassSet
|
||||
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
|
||||
eventq_index=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatAdd
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatCmp
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatCvt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatMult
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatDiv
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatSqrt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdAdd
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdAddAcc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdAlu
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdCmp
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdCvt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdMisc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdMult
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdMultAcc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdShift
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdShiftAcc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdSqrt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatAdd
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatAlu
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatCmp
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatCvt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatDiv
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMisc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMult
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMultAcc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatSqrt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.timings]
|
||||
type=MinorFUTiming
|
||||
children=opClasses
|
||||
description=FloatSimd
|
||||
eventq_index=0
|
||||
extraAssumedLat=0
|
||||
extraCommitLat=0
|
||||
extraCommitLatExpr=Null
|
||||
mask=0
|
||||
match=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
|
||||
srcRegsRelativeLats=2
|
||||
suppress=false
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
|
||||
type=MinorOpClassSet
|
||||
eventq_index=0
|
||||
opClasses=
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5]
|
||||
type=MinorFU
|
||||
children=opClasses timings
|
||||
cantForwardFromFUIndices=
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
|
||||
opLat=1
|
||||
timings=system.cpu.executeFuncUnits.funcUnits5.timings
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
|
||||
type=MinorOpClassSet
|
||||
children=opClasses0 opClasses1
|
||||
eventq_index=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=MemRead
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=MemWrite
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5.timings]
|
||||
type=MinorFUTiming
|
||||
children=opClasses
|
||||
description=Mem
|
||||
eventq_index=0
|
||||
extraAssumedLat=2
|
||||
extraCommitLat=0
|
||||
extraCommitLatExpr=Null
|
||||
mask=0
|
||||
match=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
|
||||
srcRegsRelativeLats=1
|
||||
suppress=false
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
|
||||
type=MinorOpClassSet
|
||||
eventq_index=0
|
||||
opClasses=
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits6]
|
||||
type=MinorFU
|
||||
children=opClasses
|
||||
cantForwardFromFUIndices=
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
|
||||
opLat=1
|
||||
timings=
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
|
||||
type=MinorOpClassSet
|
||||
children=opClasses0 opClasses1
|
||||
eventq_index=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=IprAccess
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=InstPrefetch
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_aa64pfr0_el1=34
|
||||
id_aa64pfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
id_pfr0=49
|
||||
id_pfr1=4113
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:268435455:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
@@ -1,29 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 11 2016 00:00:58
|
||||
gem5 started Oct 13 2016 20:43:02
|
||||
gem5 executing on e108600-lin, pid 17345
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/minor-timing
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
MCF SPEC version 1.6.I
|
||||
by Andreas Loebel
|
||||
Copyright (c) 1998,1999 ZIB Berlin
|
||||
All Rights Reserved.
|
||||
|
||||
nodes : 500
|
||||
active arcs : 1905
|
||||
simplex iterations : 1502
|
||||
flow value : 4990014995
|
||||
new implicit arcs : 23867
|
||||
active arcs : 25772
|
||||
simplex iterations : 2663
|
||||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 62552970500 because target called exit()
|
||||
@@ -1,914 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.062555 # Number of seconds simulated
|
||||
sim_ticks 62555455500 # Number of ticks simulated
|
||||
final_tick 62555455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 428742 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 430877 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 296018745 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 404460 # Number of bytes of host memory used
|
||||
host_seconds 211.32 # Real time elapsed on the host
|
||||
sim_insts 90602850 # Number of instructions simulated
|
||||
sim_ops 91054081 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 791873 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 15142788 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 15934661 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 791873 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 791873 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 791873 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 15142788 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 15934661 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 15575 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 993 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 891 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 949 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 1027 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 962 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 938 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 904 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 867 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 876 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 906 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 62555354500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 15575 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 15455 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 646.524675 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 437.465548 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 402.658643 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 259 16.82% 16.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 177 11.49% 28.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 80 5.19% 33.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 40 2.60% 50.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 67 4.35% 55.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 211097500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 503128750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 13553.61 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 32303.61 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.12 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 14028 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 4016395.15 # Average gap between requests
|
||||
system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 58540860 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 136590240 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 8764320 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 737385060 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 211641120 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 14429375100 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 15802368780 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 252.613756 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 62232966250 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::SREF 60064867500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 551102250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 223150500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 1617057250 # Time in different power states
|
||||
system.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 136410120 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 13262400 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 827323080 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 248273280 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 14377994265 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 15920556885 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 254.503090 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 62220218000 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 59760759500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 646525750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 203991750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 1814347500 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 20806620 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 17114048 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 756880 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 8968258 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 8843232 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 98.605905 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 61975 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 24793 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 1418 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 666 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.numSyscalls 442 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 125110911 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 90602850 # Number of instructions committed
|
||||
system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2181045 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.380872 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.724180 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 91054081 # Class of committed instruction
|
||||
system.cpu.tickCycles 110528679 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 14582232 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 946104 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3621.120784 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26274613 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 950200 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.651666 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 20754332500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3621.120784 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.884063 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.884063 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2198 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1666 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 55461064 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 55461064 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21605665 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21605665 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4660666 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4660666 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26266331 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26266331 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26266839 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26266839 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 906500 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 906500 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 74315 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 74315 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 980815 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 980815 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 980819 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 980819 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832236000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11832236000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760278000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2760278000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14592514000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14592514000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14592514000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14592514000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22512165 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22512165 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27247146 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27247146 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27247658 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27247658 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.659680 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.659680 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.945570 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.945570 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.947421 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14877.947421 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.886746 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14877.886746 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 943285 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3067 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 3067 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27551 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 27551 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 30618 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 30618 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 30618 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 30618 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 950197 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 950197 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 950200 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 950200 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889912000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889912000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596274500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596274500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486186500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12486186500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486356500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12486356500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034873 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.923202 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.923202 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34134.686939 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34134.686939 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.629259 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.629259 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.766681 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.766681 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 5 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 689.583421 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 27839479 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 34712.567332 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 689.583421 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.336711 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.336711 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 55681364 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 55681364 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 27839479 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 27839479 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 27839479 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 27839479 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 27839479 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 27839479 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 802 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 71421000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 71421000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 71421000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 71421000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 71421000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 71421000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27840281 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 27840281 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 27840281 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 27840281 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 27840281 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 27840281 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89053.615960 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 89053.615960 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 89053.615960 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 89053.615960 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 5 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 5 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70619000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 70619000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70619000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 70619000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70619000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 70619000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88053.615960 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88053.615960 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88053.615960 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 88053.615960 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88053.615960 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 88053.615960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 11308.105127 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1881379 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15575 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 120.794799 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.588306 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.516821 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.324509 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.345096 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15575 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475311 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15191263 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15191263 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 943285 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 943285 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 27 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 27 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903173 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 903173 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 935393 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 935420 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 935393 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 935420 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 775 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 775 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 263 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 263 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 775 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14807 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 775 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182333500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1182333500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69109000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 69109000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49239000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 49239000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 69109000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1231572500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1300681500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 69109000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1231572500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1300681500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 943285 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 943285 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903436 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 903436 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 950200 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 951002 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 950200 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 951002 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966334 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966334 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966334 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966334 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81293.557481 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81293.557481 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89172.903226 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89172.903226 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187220.532319 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187220.532319 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 83473.334617 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 83473.334617 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 774 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 774 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036893500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036893500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61295500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61295500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46236000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46236000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61295500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083129500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1144425000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61295500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083129500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1144425000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71293.557481 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71293.557481 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79193.152455 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79193.152455 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179906.614786 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179906.614786 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1897111 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 946125 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 943285 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 903436 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846504 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2848113 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 951002 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 950836 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 951002 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1891845500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1203499 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1425302994 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
||||
system.membus.snoop_filter.tot_requests 15575 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1031 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1031 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 15575 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15575 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 21782500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 82144500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,962 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
branchPred=system.cpu.branchPred
|
||||
cacheStorePorts=200
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.branchPred]
|
||||
type=BiModeBP
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=6
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=8
|
||||
write_buffers=16
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IntDiv
|
||||
opLat=12
|
||||
pipelined=false
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=MemRead
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMemRead
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMemWrite
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdAdd
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdAddAcc
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdAlu
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdCmp
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdCvt
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdMisc
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdMult
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdMultAcc
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdShift
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdShiftAcc
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdSqrt
|
||||
opLat=9
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatAdd
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatAlu
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatCmp
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatCvt
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatDiv
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMisc
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMult
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=9
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
pipelined=false
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
pipelined=false
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList26]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMultAcc
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList27]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMisc
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=1
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=1
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=8
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=1
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=1
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=Cache
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_excl
|
||||
data_latency=12
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tag_latency=12
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=8
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
cache_snoop=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
degree=8
|
||||
eventq_index=0
|
||||
latency=1
|
||||
max_conf=7
|
||||
min_conf=0
|
||||
on_data=true
|
||||
on_inst=true
|
||||
on_miss=false
|
||||
on_read=true
|
||||
on_write=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
queue_filter=true
|
||||
queue_size=32
|
||||
queue_squash=true
|
||||
start_conf=4
|
||||
sys=system
|
||||
table_assoc=4
|
||||
table_sets=16
|
||||
tag_prefetch=true
|
||||
thresh_conf=4
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=12
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
tag_latency=12
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=55300000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:268435455:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,999 +0,0 @@
|
||||
()
|
||||
500
|
||||
()
|
||||
499
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
478
|
||||
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|
||||
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|
||||
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|
||||
476
|
||||
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|
||||
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|
||||
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|
||||
474
|
||||
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|
||||
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|
||||
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|
||||
472
|
||||
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|
||||
471
|
||||
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|
||||
469
|
||||
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|
||||
468
|
||||
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|
||||
467
|
||||
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|
||||
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|
||||
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|
||||
465
|
||||
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|
||||
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|
||||
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|
||||
463
|
||||
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|
||||
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|
||||
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|
||||
461
|
||||
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|
||||
460
|
||||
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|
||||
459
|
||||
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|
||||
458
|
||||
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|
||||
457
|
||||
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|
||||
455
|
||||
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|
||||
454
|
||||
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|
||||
452
|
||||
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|
||||
451
|
||||
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|
||||
450
|
||||
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|
||||
449
|
||||
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|
||||
448
|
||||
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|
||||
446
|
||||
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|
||||
445
|
||||
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|
||||
444
|
||||
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|
||||
443
|
||||
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|
||||
442
|
||||
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|
||||
440
|
||||
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|
||||
439
|
||||
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|
||||
438
|
||||
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|
||||
436
|
||||
()
|
||||
435
|
||||
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|
||||
433
|
||||
()
|
||||
432
|
||||
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|
||||
431
|
||||
()
|
||||
428
|
||||
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|
||||
427
|
||||
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|
||||
425
|
||||
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|
||||
424
|
||||
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|
||||
423
|
||||
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|
||||
420
|
||||
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|
||||
419
|
||||
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|
||||
416
|
||||
()
|
||||
414
|
||||
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|
||||
413
|
||||
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|
||||
412
|
||||
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|
||||
407
|
||||
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|
||||
406
|
||||
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|
||||
405
|
||||
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|
||||
404
|
||||
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|
||||
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|
||||
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|
||||
402
|
||||
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|
||||
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|
||||
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|
||||
400
|
||||
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|
||||
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|
||||
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|
||||
398
|
||||
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|
||||
396
|
||||
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|
||||
395
|
||||
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|
||||
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|
||||
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|
||||
392
|
||||
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|
||||
390
|
||||
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|
||||
389
|
||||
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|
||||
388
|
||||
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|
||||
387
|
||||
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|
||||
386
|
||||
()
|
||||
385
|
||||
()
|
||||
384
|
||||
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|
||||
383
|
||||
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|
||||
382
|
||||
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|
||||
381
|
||||
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|
||||
380
|
||||
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|
||||
379
|
||||
()
|
||||
377
|
||||
()
|
||||
375
|
||||
()
|
||||
374
|
||||
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|
||||
373
|
||||
()
|
||||
372
|
||||
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|
||||
371
|
||||
()
|
||||
370
|
||||
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|
||||
369
|
||||
()
|
||||
368
|
||||
()
|
||||
366
|
||||
()
|
||||
365
|
||||
()
|
||||
364
|
||||
()
|
||||
362
|
||||
()
|
||||
361
|
||||
()
|
||||
360
|
||||
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|
||||
359
|
||||
()
|
||||
358
|
||||
()
|
||||
357
|
||||
()
|
||||
356
|
||||
()
|
||||
355
|
||||
()
|
||||
354
|
||||
()
|
||||
352
|
||||
()
|
||||
350
|
||||
()
|
||||
347
|
||||
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|
||||
344
|
||||
()
|
||||
342
|
||||
()
|
||||
341
|
||||
()
|
||||
340
|
||||
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|
||||
339
|
||||
()
|
||||
338
|
||||
()
|
||||
332
|
||||
()
|
||||
325
|
||||
()
|
||||
320
|
||||
***
|
||||
345
|
||||
()
|
||||
319
|
||||
***
|
||||
497
|
||||
()
|
||||
318
|
||||
***
|
||||
349
|
||||
()
|
||||
317
|
||||
***
|
||||
408
|
||||
()
|
||||
316
|
||||
***
|
||||
324
|
||||
()
|
||||
315
|
||||
***
|
||||
328
|
||||
()
|
||||
314
|
||||
***
|
||||
335
|
||||
()
|
||||
313
|
||||
***
|
||||
378
|
||||
()
|
||||
312
|
||||
***
|
||||
426
|
||||
()
|
||||
311
|
||||
***
|
||||
411
|
||||
()
|
||||
304
|
||||
***
|
||||
343
|
||||
()
|
||||
303
|
||||
***
|
||||
417
|
||||
()
|
||||
302
|
||||
***
|
||||
485
|
||||
()
|
||||
301
|
||||
***
|
||||
363
|
||||
()
|
||||
300
|
||||
***
|
||||
376
|
||||
()
|
||||
299
|
||||
***
|
||||
333
|
||||
()
|
||||
292
|
||||
***
|
||||
337
|
||||
()
|
||||
291
|
||||
***
|
||||
409
|
||||
()
|
||||
290
|
||||
***
|
||||
421
|
||||
()
|
||||
289
|
||||
***
|
||||
437
|
||||
()
|
||||
288
|
||||
***
|
||||
430
|
||||
()
|
||||
287
|
||||
***
|
||||
348
|
||||
()
|
||||
286
|
||||
***
|
||||
326
|
||||
()
|
||||
284
|
||||
()
|
||||
282
|
||||
***
|
||||
308
|
||||
()
|
||||
279
|
||||
***
|
||||
297
|
||||
***
|
||||
305
|
||||
()
|
||||
278
|
||||
()
|
||||
277
|
||||
***
|
||||
307
|
||||
()
|
||||
276
|
||||
***
|
||||
296
|
||||
()
|
||||
273
|
||||
()
|
||||
271
|
||||
()
|
||||
265
|
||||
()
|
||||
246
|
||||
***
|
||||
267
|
||||
()
|
||||
245
|
||||
***
|
||||
280
|
||||
()
|
||||
244
|
||||
***
|
||||
391
|
||||
()
|
||||
243
|
||||
***
|
||||
330
|
||||
()
|
||||
242
|
||||
***
|
||||
456
|
||||
()
|
||||
241
|
||||
***
|
||||
346
|
||||
()
|
||||
240
|
||||
***
|
||||
483
|
||||
()
|
||||
239
|
||||
***
|
||||
260
|
||||
()
|
||||
238
|
||||
***
|
||||
261
|
||||
()
|
||||
237
|
||||
***
|
||||
262
|
||||
***
|
||||
294
|
||||
()
|
||||
236
|
||||
***
|
||||
253
|
||||
()
|
||||
229
|
||||
***
|
||||
397
|
||||
()
|
||||
228
|
||||
***
|
||||
298
|
||||
()
|
||||
227
|
||||
***
|
||||
415
|
||||
()
|
||||
226
|
||||
***
|
||||
264
|
||||
()
|
||||
224
|
||||
***
|
||||
232
|
||||
()
|
||||
222
|
||||
***
|
||||
233
|
||||
()
|
||||
217
|
||||
***
|
||||
250
|
||||
()
|
||||
211
|
||||
***
|
||||
331
|
||||
()
|
||||
210
|
||||
***
|
||||
394
|
||||
()
|
||||
209
|
||||
***
|
||||
410
|
||||
()
|
||||
208
|
||||
***
|
||||
321
|
||||
()
|
||||
207
|
||||
***
|
||||
327
|
||||
()
|
||||
206
|
||||
***
|
||||
309
|
||||
()
|
||||
199
|
||||
***
|
||||
259
|
||||
()
|
||||
198
|
||||
***
|
||||
219
|
||||
()
|
||||
197
|
||||
***
|
||||
220
|
||||
()
|
||||
195
|
||||
***
|
||||
429
|
||||
()
|
||||
194
|
||||
***
|
||||
470
|
||||
()
|
||||
193
|
||||
***
|
||||
274
|
||||
()
|
||||
191
|
||||
***
|
||||
203
|
||||
()
|
||||
190
|
||||
***
|
||||
263
|
||||
()
|
||||
189
|
||||
215
|
||||
***
|
||||
230
|
||||
()
|
||||
188
|
||||
***
|
||||
266
|
||||
***
|
||||
295
|
||||
()
|
||||
182
|
||||
***
|
||||
329
|
||||
()
|
||||
181
|
||||
***
|
||||
351
|
||||
()
|
||||
180
|
||||
***
|
||||
441
|
||||
()
|
||||
179
|
||||
***
|
||||
453
|
||||
()
|
||||
178
|
||||
***
|
||||
418
|
||||
()
|
||||
177
|
||||
***
|
||||
353
|
||||
()
|
||||
176
|
||||
***
|
||||
422
|
||||
()
|
||||
175
|
||||
***
|
||||
225
|
||||
***
|
||||
255
|
||||
()
|
||||
174
|
||||
***
|
||||
269
|
||||
()
|
||||
173
|
||||
***
|
||||
214
|
||||
()
|
||||
172
|
||||
***
|
||||
186
|
||||
()
|
||||
171
|
||||
***
|
||||
447
|
||||
()
|
||||
170
|
||||
***
|
||||
270
|
||||
***
|
||||
306
|
||||
()
|
||||
169
|
||||
***
|
||||
336
|
||||
()
|
||||
168
|
||||
***
|
||||
285
|
||||
()
|
||||
165
|
||||
***
|
||||
249
|
||||
()
|
||||
146
|
||||
***
|
||||
154
|
||||
()
|
||||
143
|
||||
***
|
||||
334
|
||||
()
|
||||
142
|
||||
***
|
||||
216
|
||||
***
|
||||
257
|
||||
()
|
||||
141
|
||||
***
|
||||
167
|
||||
***
|
||||
251
|
||||
()
|
||||
140
|
||||
***
|
||||
162
|
||||
***
|
||||
293
|
||||
()
|
||||
139
|
||||
***
|
||||
158
|
||||
()
|
||||
137
|
||||
***
|
||||
166
|
||||
***
|
||||
201
|
||||
()
|
||||
136
|
||||
***
|
||||
160
|
||||
()
|
||||
134
|
||||
***
|
||||
221
|
||||
()
|
||||
132
|
||||
***
|
||||
213
|
||||
()
|
||||
131
|
||||
***
|
||||
187
|
||||
()
|
||||
129
|
||||
***
|
||||
235
|
||||
()
|
||||
128
|
||||
***
|
||||
153
|
||||
()
|
||||
127
|
||||
***
|
||||
156
|
||||
()
|
||||
126
|
||||
***
|
||||
159
|
||||
***
|
||||
218
|
||||
()
|
||||
125
|
||||
***
|
||||
155
|
||||
()
|
||||
124
|
||||
***
|
||||
157
|
||||
()
|
||||
123
|
||||
***
|
||||
152
|
||||
()
|
||||
116
|
||||
***
|
||||
135
|
||||
***
|
||||
163
|
||||
()
|
||||
115
|
||||
***
|
||||
133
|
||||
***
|
||||
204
|
||||
***
|
||||
248
|
||||
()
|
||||
114
|
||||
***
|
||||
192
|
||||
***
|
||||
212
|
||||
()
|
||||
113
|
||||
***
|
||||
268
|
||||
()
|
||||
112
|
||||
***
|
||||
367
|
||||
()
|
||||
111
|
||||
***
|
||||
272
|
||||
()
|
||||
110
|
||||
***
|
||||
434
|
||||
()
|
||||
109
|
||||
***
|
||||
323
|
||||
()
|
||||
108
|
||||
***
|
||||
281
|
||||
()
|
||||
107
|
||||
***
|
||||
144
|
||||
***
|
||||
148
|
||||
()
|
||||
106
|
||||
***
|
||||
275
|
||||
()
|
||||
105
|
||||
***
|
||||
196
|
||||
***
|
||||
254
|
||||
()
|
||||
104
|
||||
***
|
||||
138
|
||||
***
|
||||
161
|
||||
()
|
||||
103
|
||||
***
|
||||
310
|
||||
()
|
||||
102
|
||||
***
|
||||
223
|
||||
***
|
||||
252
|
||||
()
|
||||
80
|
||||
()
|
||||
70
|
||||
()
|
||||
69
|
||||
()
|
||||
68
|
||||
()
|
||||
66
|
||||
()
|
||||
64
|
||||
()
|
||||
62
|
||||
***
|
||||
256
|
||||
()
|
||||
61
|
||||
***
|
||||
93
|
||||
()
|
||||
59
|
||||
***
|
||||
120
|
||||
()
|
||||
58
|
||||
()
|
||||
57
|
||||
***
|
||||
183
|
||||
()
|
||||
55
|
||||
()
|
||||
54
|
||||
()
|
||||
52
|
||||
***
|
||||
147
|
||||
()
|
||||
51
|
||||
***
|
||||
118
|
||||
()
|
||||
50
|
||||
***
|
||||
83
|
||||
()
|
||||
49
|
||||
***
|
||||
98
|
||||
()
|
||||
48
|
||||
***
|
||||
99
|
||||
()
|
||||
47
|
||||
()
|
||||
46
|
||||
***
|
||||
184
|
||||
()
|
||||
45
|
||||
***
|
||||
121
|
||||
()
|
||||
44
|
||||
()
|
||||
43
|
||||
***
|
||||
88
|
||||
()
|
||||
42
|
||||
***
|
||||
122
|
||||
()
|
||||
41
|
||||
***
|
||||
91
|
||||
()
|
||||
40
|
||||
***
|
||||
96
|
||||
()
|
||||
38
|
||||
***
|
||||
100
|
||||
()
|
||||
37
|
||||
***
|
||||
149
|
||||
()
|
||||
36
|
||||
***
|
||||
74
|
||||
()
|
||||
35
|
||||
***
|
||||
258
|
||||
()
|
||||
34
|
||||
***
|
||||
151
|
||||
()
|
||||
33
|
||||
***
|
||||
85
|
||||
()
|
||||
32
|
||||
()
|
||||
31
|
||||
***
|
||||
94
|
||||
()
|
||||
30
|
||||
***
|
||||
97
|
||||
()
|
||||
29
|
||||
***
|
||||
90
|
||||
()
|
||||
28
|
||||
***
|
||||
89
|
||||
()
|
||||
27
|
||||
***
|
||||
92
|
||||
()
|
||||
26
|
||||
***
|
||||
72
|
||||
***
|
||||
247
|
||||
()
|
||||
25
|
||||
***
|
||||
86
|
||||
()
|
||||
24
|
||||
***
|
||||
82
|
||||
()
|
||||
23
|
||||
***
|
||||
87
|
||||
***
|
||||
117
|
||||
()
|
||||
22
|
||||
***
|
||||
76
|
||||
***
|
||||
119
|
||||
()
|
||||
21
|
||||
***
|
||||
84
|
||||
()
|
||||
20
|
||||
***
|
||||
78
|
||||
()
|
||||
19
|
||||
***
|
||||
73
|
||||
()
|
||||
18
|
||||
***
|
||||
81
|
||||
()
|
||||
17
|
||||
***
|
||||
65
|
||||
()
|
||||
16
|
||||
***
|
||||
63
|
||||
***
|
||||
101
|
||||
()
|
||||
15
|
||||
***
|
||||
71
|
||||
()
|
||||
14
|
||||
***
|
||||
75
|
||||
()
|
||||
13
|
||||
***
|
||||
322
|
||||
()
|
||||
12
|
||||
***
|
||||
77
|
||||
()
|
||||
11
|
||||
***
|
||||
283
|
||||
()
|
||||
10
|
||||
***
|
||||
79
|
||||
()
|
||||
9
|
||||
***
|
||||
145
|
||||
***
|
||||
150
|
||||
()
|
||||
8
|
||||
***
|
||||
67
|
||||
()
|
||||
7
|
||||
***
|
||||
60
|
||||
***
|
||||
231
|
||||
()
|
||||
6
|
||||
***
|
||||
56
|
||||
***
|
||||
234
|
||||
()
|
||||
5
|
||||
***
|
||||
164
|
||||
***
|
||||
202
|
||||
()
|
||||
4
|
||||
***
|
||||
53
|
||||
()
|
||||
3
|
||||
***
|
||||
130
|
||||
***
|
||||
185
|
||||
***
|
||||
200
|
||||
()
|
||||
2
|
||||
***
|
||||
205
|
||||
()
|
||||
1
|
||||
***
|
||||
39
|
||||
***
|
||||
95
|
||||
@@ -1,5 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user