misc,python: Add isort hook to pre-commit (#431)

src/arch/amdgpu/common/X86GPUTLB.py

@@ -28,10 +28,9 @@
 # POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-
-from m5.objects.ClockedObject import ClockedObject
 from m5.SimObject import SimObject
 
 

src/arch/amdgpu/vega/VegaGPUTLB.py

@@ -28,11 +28,10 @@
 # POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
+from m5.objects.AMDGPU import AMDGPUDevice
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-
-from m5.objects.ClockedObject import ClockedObject
-from m5.objects.AMDGPU import AMDGPUDevice
 from m5.SimObject import SimObject
 
 

src/arch/arm/ArmCPU.py

@@ -23,18 +23,17 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.proxy import Self
-
-from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
-from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
-from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
-from m5.objects.BaseO3CPU import BaseO3CPU
-from m5.objects.BaseO3Checker import BaseO3Checker
-from m5.objects.BaseMinorCPU import BaseMinorCPU
 from m5.objects.ArmDecoder import ArmDecoder
-from m5.objects.ArmMMU import ArmMMU
 from m5.objects.ArmInterrupts import ArmInterrupts
 from m5.objects.ArmISA import ArmISA
+from m5.objects.ArmMMU import ArmMMU
+from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
+from m5.objects.BaseMinorCPU import BaseMinorCPU
+from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
+from m5.objects.BaseO3Checker import BaseO3Checker
+from m5.objects.BaseO3CPU import BaseO3CPU
+from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
+from m5.proxy import Self
 
 
 class ArmCPU:

src/arch/arm/ArmDecoder.py

@@ -35,8 +35,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.InstDecoder import InstDecoder
+from m5.params import *
 
 
 class ArmDecoder(InstDecoder):

src/arch/arm/ArmFsWorkload.py

@@ -33,10 +33,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-from m5.options import *
-from m5.SimObject import *
 from m5.objects.Workload import KernelWorkload
+from m5.options import *
+from m5.params import *
+from m5.SimObject import *
 
 
 class ArmMachineType(Enum):

src/arch/arm/ArmISA.py

@@ -33,13 +33,16 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ArmPMU import ArmPMU
+from m5.objects.ArmSystem import (
+    ArmRelease,
+    SmeVectorLength,
+    SveVectorLength,
+)
+from m5.objects.BaseISA import BaseISA
 from m5.params import *
 from m5.proxy import *
-
 from m5.SimObject import SimObject
-from m5.objects.ArmPMU import ArmPMU
-from m5.objects.ArmSystem import SveVectorLength, SmeVectorLength, ArmRelease
-from m5.objects.BaseISA import BaseISA
 
 
 # Enum for DecoderFlavor

src/arch/arm/ArmMMU.py

@@ -36,7 +36,10 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.objects.ArmSystem import ArmRelease
-from m5.objects.ArmTLB import ArmTLB, ArmStage2TLB
+from m5.objects.ArmTLB import (
+    ArmStage2TLB,
+    ArmTLB,
+)
 from m5.objects.BaseMMU import BaseMMU
 from m5.objects.ClockedObject import ClockedObject
 from m5.params import *

src/arch/arm/ArmNativeTrace.py

@@ -24,9 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.CPUTracers import NativeTrace
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class ArmNativeTrace(NativeTrace):

src/arch/arm/ArmPMU.py

@@ -35,11 +35,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
-from m5.SimObject import *
+from m5.objects.Gic import (
+    ArmInterruptPin,
+    ArmPPI,
+)
 from m5.params import *
 from m5.params import isNullPointer
 from m5.proxy import *
-from m5.objects.Gic import ArmInterruptPin, ArmPPI
+from m5.SimObject import *
 from m5.util.fdthelper import *
 
 

src/arch/arm/ArmSeWorkload.py

@@ -23,9 +23,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.Workload import SEWorkload
+from m5.params import *
 
 
 class ArmSEWorkload(SEWorkload):

src/arch/arm/ArmSemihosting.py

@@ -33,11 +33,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-from m5.SimObject import *
-
 from m5.objects.Serial import SerialDevice
 from m5.objects.Terminal import Terminal
+from m5.params import *
+from m5.SimObject import *
 
 
 class ArmSemihosting(SimObject):

src/arch/arm/ArmSystem.py

@@ -33,16 +33,15 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
+from typing import Any
+
+from m5.objects.ArmSemihosting import ArmSemihosting
+from m5.objects.System import System
 from m5.options import *
+from m5.params import *
 from m5.SimObject import *
 from m5.util.fdthelper import *
 
-from m5.objects.System import System
-from m5.objects.ArmSemihosting import ArmSemihosting
-
-from typing import Any
-
 
 class SveVectorLength(UInt8):
     min = 1

src/arch/arm/ArmTLB.py

@@ -35,10 +35,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
+from m5.objects.BaseTLB import BaseTLB
 from m5.params import *
 from m5.proxy import *
-from m5.objects.BaseTLB import BaseTLB
+from m5.SimObject import SimObject
 
 
 class ArmLookupLevel(Enum):

src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py

@@ -23,20 +23,25 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ArmInterrupts import ArmInterrupts
+from m5.objects.ArmISA import ArmISA
+from m5.objects.FastModel import (
+    AmbaInitiatorSocket,
+    AmbaTargetSocket,
+)
+from m5.objects.FastModelGIC import Gicv3CommsTargetSocket
+from m5.objects.Gic import ArmPPI
+from m5.objects.IntPin import IntSinkPin
+from m5.objects.Iris import IrisBaseCPU
+from m5.objects.ResetPort import ResetResponsePort
+from m5.objects.SystemC import SystemC_ScModule
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-
-from m5.objects.ArmInterrupts import ArmInterrupts
-from m5.objects.ArmISA import ArmISA
-from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
-from m5.objects.FastModelGIC import Gicv3CommsTargetSocket
-from m5.objects.ResetPort import ResetResponsePort
-from m5.objects.IntPin import IntSinkPin
-from m5.objects.Gic import ArmPPI
-from m5.objects.Iris import IrisBaseCPU
-from m5.objects.SystemC import SystemC_ScModule
-from m5.util.fdthelper import FdtNode, FdtPropertyWords
+from m5.util.fdthelper import (
+    FdtNode,
+    FdtPropertyWords,
+)
 
 
 class FastModelCortexA76(IrisBaseCPU):

src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py

@@ -23,18 +23,24 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ArmInterrupts import ArmInterrupts
+from m5.objects.ArmISA import ArmISA
+from m5.objects.FastModel import (
+    AmbaInitiatorSocket,
+    AmbaTargetSocket,
+)
+from m5.objects.IntPin import (
+    IntSinkPin,
+    IntSourcePin,
+    VectorIntSinkPin,
+)
+from m5.objects.Iris import IrisBaseCPU
+from m5.objects.ResetPort import ResetResponsePort
+from m5.objects.SystemC import SystemC_ScModule
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
-from m5.objects.ArmInterrupts import ArmInterrupts
-from m5.objects.ArmISA import ArmISA
-from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
-from m5.objects.ResetPort import ResetResponsePort
-from m5.objects.IntPin import IntSourcePin, IntSinkPin, VectorIntSinkPin
-from m5.objects.Iris import IrisBaseCPU
-from m5.objects.SystemC import SystemC_ScModule
-
 
 class FastModelCortexR52(IrisBaseCPU):
     type = "FastModelCortexR52"

src/arch/arm/fastmodel/FastModel.py

@@ -23,12 +23,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.SystemC import SystemC_ScModule
+from m5.objects.Tlm import (
+    TlmInitiatorSocket,
+    TlmTargetSocket,
+)
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.SystemC import SystemC_ScModule
-from m5.objects.Tlm import TlmInitiatorSocket, TlmTargetSocket
-
 
 def AMBA_TARGET_ROLE(width):
     return "AMBA TARGET %d" % width

src/arch/arm/fastmodel/GIC/FastModelGIC.py

@@ -35,15 +35,17 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-from m5.util.fdthelper import *
-from m5.SimObject import SimObject
-
-from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
+from m5.objects.FastModel import (
+    AmbaInitiatorSocket,
+    AmbaTargetSocket,
+)
 from m5.objects.Gic import BaseGic
 from m5.objects.IntPin import VectorIntSourcePin
 from m5.objects.ResetPort import ResetResponsePort
 from m5.objects.SystemC import SystemC_ScModule
+from m5.params import *
+from m5.SimObject import SimObject
+from m5.util.fdthelper import *
 
 GICV3_COMMS_TARGET_ROLE = "GICV3 COMMS TARGET"
 GICV3_COMMS_INITIATOR_ROLE = "GICV3 COMMS INITIATOR"

src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py

@@ -23,11 +23,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
+from m5.objects.FastModel import (
+    AmbaInitiatorSocket,
+    AmbaTargetSocket,
+)
 from m5.objects.IntPin import IntSourcePin
 from m5.objects.ResetPort import ResetResponsePort
 from m5.objects.SystemC import SystemC_ScModule
+from m5.params import *
 
 
 class FastModelPL330(SystemC_ScModule):

src/arch/arm/fastmodel/arm_fast_model.py

@@ -29,6 +29,7 @@ import os
 import socket
 
 from m5.defines import buildEnv
+
 import _m5.arm_fast_model
 
 ARM_LICENSE_ENV = "ARMLMD_LICENSE_FILE"

src/arch/arm/fastmodel/iris/Iris.py

@@ -35,14 +35,13 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-from m5.proxy import *
-
 from m5.objects.BaseCPU import BaseCPU
 from m5.objects.BaseInterrupts import BaseInterrupts
 from m5.objects.BaseISA import BaseISA
-from m5.objects.BaseTLB import BaseTLB
 from m5.objects.BaseMMU import BaseMMU
+from m5.objects.BaseTLB import BaseTLB
+from m5.params import *
+from m5.proxy import *
 
 
 class IrisTLB(BaseTLB):

src/arch/arm/fastmodel/reset_controller/FastModelResetControllerExample.py

@@ -23,12 +23,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-from m5.proxy import *
-
 from m5.objects.Device import BasicPioDevice
 from m5.objects.IntPin import IntSourcePin
 from m5.objects.Iris import IrisBaseCPU
+from m5.params import *
+from m5.proxy import *
 
 
 class FastModelResetControllerExample(BasicPioDevice):

src/arch/arm/kvm/ArmKvmCPU.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.BaseKvmCPU import BaseKvmCPU
+from m5.params import *
 
 
 class ArmKvmCPU(BaseKvmCPU):

src/arch/arm/kvm/ArmV8KvmCPU.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.BaseArmKvmCPU import BaseArmKvmCPU
+from m5.params import *
 
 
 class ArmV8KvmCPU(BaseArmKvmCPU):

src/arch/arm/kvm/BaseArmKvmCPU.py

@@ -33,10 +33,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.ArmCPU import ArmCPU
 from m5.objects.ArmMMU import ArmMMU
 from m5.objects.BaseKvmCPU import BaseKvmCPU
+from m5.params import *
 
 
 class BaseArmKvmCPU(BaseKvmCPU, ArmCPU):

src/arch/arm/kvm/KvmGic.py

@@ -33,11 +33,13 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.Gic import (
+    GicV2,
+    Gicv3,
+)
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.Gic import GicV2, Gicv3
-
 
 class MuxingKvmGicV2(GicV2):
     type = "MuxingKvmGicV2"

src/arch/arm/tracers/ArmCapstone.py

@@ -33,9 +33,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.Capstone import CapstoneDisassembler
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class ArmCapstoneDisassembler(CapstoneDisassembler):

src/arch/arm/tracers/TarmacTrace.py

@@ -33,9 +33,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.InstTracer import InstTracer
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class TarmacParser(InstTracer):

src/arch/isa_parser/isa_parser.py

@@ -46,6 +46,7 @@ import traceback
 from types import *
 
 from grammar import Grammar
+
 from .operand_list import *
 from .operand_types import *
 from .util import *

src/arch/isa_parser/operand_list.py

@@ -37,8 +37,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .util import assignRE, commentRE, stringRE
-from .util import error
+from .util import (
+    assignRE,
+    commentRE,
+    error,
+    stringRE,
+)
 
 
 class OperandList:

src/arch/micro_asm.py

@@ -25,15 +25,17 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import os
-import sys
 import re
+import sys
 import traceback
 
 # get type names
 from types import *
 
-from ply import lex
-from ply import yacc
+from ply import (
+    lex,
+    yacc,
+)
 
 ##########################################################################
 #

src/arch/micro_asm_test.py

@@ -24,7 +24,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from micro_asm import MicroAssembler, CombinationalMacroop, RomMacroop, Rom
+from micro_asm import (
+    CombinationalMacroop,
+    MicroAssembler,
+    Rom,
+    RomMacroop,
+)
 
 
 class Bah:

src/arch/mips/MipsCPU.py

@@ -24,14 +24,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
-from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
-from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
-from m5.objects.BaseO3CPU import BaseO3CPU
 from m5.objects.BaseMinorCPU import BaseMinorCPU
+from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
+from m5.objects.BaseO3CPU import BaseO3CPU
+from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
 from m5.objects.MipsDecoder import MipsDecoder
-from m5.objects.MipsMMU import MipsMMU
 from m5.objects.MipsInterrupts import MipsInterrupts
 from m5.objects.MipsISA import MipsISA
+from m5.objects.MipsMMU import MipsMMU
 
 
 class MipsCPU:

src/arch/mips/MipsISA.py

@@ -33,11 +33,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.BaseISA import BaseISA
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.BaseISA import BaseISA
-
 
 class MipsISA(BaseISA):
     type = "MipsISA"

src/arch/mips/MipsSeWorkload.py

@@ -23,9 +23,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.Workload import SEWorkload
+from m5.params import *
 
 
 class MipsSEWorkload(SEWorkload):

src/arch/mips/MipsTLB.py

@@ -26,10 +26,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
-
 from m5.objects.BaseTLB import BaseTLB
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class MipsTLB(BaseTLB):

src/arch/power/PowerCPU.py

@@ -24,14 +24,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
-from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
-from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
-from m5.objects.BaseO3CPU import BaseO3CPU
 from m5.objects.BaseMinorCPU import BaseMinorCPU
+from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
+from m5.objects.BaseO3CPU import BaseO3CPU
+from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
 from m5.objects.PowerDecoder import PowerDecoder
-from m5.objects.PowerMMU import PowerMMU
 from m5.objects.PowerInterrupts import PowerInterrupts
 from m5.objects.PowerISA import PowerISA
+from m5.objects.PowerMMU import PowerMMU
 
 
 class PowerCPU:

src/arch/power/PowerSeWorkload.py

@@ -23,9 +23,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.Workload import SEWorkload
+from m5.params import *
 
 
 class PowerSEWorkload(SEWorkload):

src/arch/power/PowerTLB.py

@@ -26,10 +26,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
-
 from m5.objects.BaseTLB import BaseTLB
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class PowerTLB(BaseTLB):

src/arch/riscv/PMAChecker.py

@@ -35,9 +35,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
+from m5.SimObject import SimObject
 
 
 class PMAChecker(SimObject):

src/arch/riscv/PMP.py

@@ -24,9 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
+from m5.SimObject import SimObject
 
 
 class PMP(SimObject):

src/arch/riscv/RiscvCPU.py

@@ -24,14 +24,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
-from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
-from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
-from m5.objects.BaseO3CPU import BaseO3CPU
 from m5.objects.BaseMinorCPU import BaseMinorCPU
+from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
+from m5.objects.BaseO3CPU import BaseO3CPU
+from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
 from m5.objects.RiscvDecoder import RiscvDecoder
-from m5.objects.RiscvMMU import RiscvMMU
 from m5.objects.RiscvInterrupts import RiscvInterrupts
 from m5.objects.RiscvISA import RiscvISA
+from m5.objects.RiscvMMU import RiscvMMU
 
 
 class RiscvCPU:

src/arch/riscv/RiscvFsWorkload.py

@@ -27,10 +27,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.System import System
-from m5.objects.Workload import Workload, KernelWorkload
+from m5.objects.Workload import (
+    KernelWorkload,
+    Workload,
+)
+from m5.params import *
 
 
 class RiscvBareMetal(Workload):

src/arch/riscv/RiscvISA.py

@@ -39,9 +39,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import Enum, UInt32
-from m5.params import Param
 from m5.objects.BaseISA import BaseISA
+from m5.params import (
+    Enum,
+    Param,
+    UInt32,
+)
 
 
 class RiscvVectorLength(UInt32):

src/arch/riscv/RiscvMMU.py

@@ -35,12 +35,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.BaseMMU import BaseMMU
-from m5.objects.RiscvTLB import RiscvTLB
 from m5.objects.PMAChecker import PMAChecker
 from m5.objects.PMP import PMP
+from m5.objects.RiscvTLB import RiscvTLB
+from m5.params import *
 
 
 class RiscvMMU(BaseMMU):

src/arch/riscv/RiscvSeWorkload.py

@@ -23,9 +23,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.Workload import SEWorkload
+from m5.params import *
 
 
 class RiscvSEWorkload(SEWorkload):

src/arch/riscv/RiscvTLB.py

@@ -28,11 +28,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-from m5.proxy import *
-
 from m5.objects.BaseTLB import BaseTLB
 from m5.objects.ClockedObject import ClockedObject
+from m5.params import *
+from m5.proxy import *
 
 
 class RiscvPagetableWalker(ClockedObject):

src/arch/sparc/SparcCPU.py

@@ -24,14 +24,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
-from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
-from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
-from m5.objects.BaseO3CPU import BaseO3CPU
 from m5.objects.BaseMinorCPU import BaseMinorCPU
+from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
+from m5.objects.BaseO3CPU import BaseO3CPU
+from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
 from m5.objects.SparcDecoder import SparcDecoder
-from m5.objects.SparcMMU import SparcMMU
 from m5.objects.SparcInterrupts import SparcInterrupts
 from m5.objects.SparcISA import SparcISA
+from m5.objects.SparcMMU import SparcMMU
 
 
 class SparcCPU:

src/arch/sparc/SparcFsWorkload.py

@@ -24,9 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.Workload import Workload
+from m5.params import *
 
 
 class SparcFsWorkload(Workload):

src/arch/sparc/SparcMMU.py

@@ -35,10 +35,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.BaseMMU import BaseMMU
 from m5.objects.SparcTLB import SparcTLB
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class SparcMMU(BaseMMU):

src/arch/sparc/SparcNativeTrace.py

@@ -24,10 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
-
 from m5.objects.CPUTracers import NativeTrace
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class SparcNativeTrace(NativeTrace):

src/arch/sparc/SparcSeWorkload.py

@@ -23,9 +23,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.Workload import SEWorkload
+from m5.params import *
 
 
 class SparcSEWorkload(SEWorkload):

src/arch/sparc/SparcTLB.py

@@ -24,10 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
-
 from m5.objects.BaseTLB import BaseTLB
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class SparcTLB(BaseTLB):

src/arch/x86/X86CPU.py

@@ -23,19 +23,18 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.proxy import Self
-
 from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
-from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
-from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
-from m5.objects.BaseO3CPU import BaseO3CPU
 from m5.objects.BaseMinorCPU import BaseMinorCPU
+from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
+from m5.objects.BaseO3CPU import BaseO3CPU
+from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
 from m5.objects.FuncUnit import *
 from m5.objects.FUPool import *
 from m5.objects.X86Decoder import X86Decoder
-from m5.objects.X86MMU import X86MMU
-from m5.objects.X86LocalApic import X86LocalApic
 from m5.objects.X86ISA import X86ISA
+from m5.objects.X86LocalApic import X86LocalApic
+from m5.objects.X86MMU import X86MMU
+from m5.proxy import Self
 
 
 class X86CPU:

src/arch/x86/X86FsWorkload.py

@@ -33,13 +33,21 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
-from m5.objects.E820 import X86E820Table, X86E820Entry
-from m5.objects.SMBios import X86SMBiosSMBiosTable
-from m5.objects.IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable
 from m5.objects.ACPI import X86ACPIRSDP
-from m5.objects.Workload import KernelWorkload, Workload
+from m5.objects.E820 import (
+    X86E820Entry,
+    X86E820Table,
+)
+from m5.objects.IntelMP import (
+    X86IntelMPConfigTable,
+    X86IntelMPFloatingPointer,
+)
+from m5.objects.SMBios import X86SMBiosSMBiosTable
+from m5.objects.Workload import (
+    KernelWorkload,
+    Workload,
+)
+from m5.params import *
 
 
 class X86BareMetalWorkload(Workload):

src/arch/x86/X86LocalApic.py

@@ -37,12 +37,11 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
-from m5.params import *
-from m5.proxy import *
-
 from m5.objects.BaseInterrupts import BaseInterrupts
 from m5.objects.ClockDomain import DerivedClockDomain
 from m5.objects.IntPin import IntSinkPin
+from m5.params import *
+from m5.proxy import *
 
 
 class X86LocalApic(BaseInterrupts):

src/arch/x86/X86NativeTrace.py

@@ -24,10 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
-
 from m5.objects.CPUTracers import NativeTrace
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class X86NativeTrace(NativeTrace):

src/arch/x86/X86SeWorkload.py

@@ -23,9 +23,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.Workload import SEWorkload
+from m5.params import *
 
 
 class X86EmuLinux(SEWorkload):

src/arch/x86/X86TLB.py

@@ -33,11 +33,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-from m5.proxy import *
-
 from m5.objects.BaseTLB import BaseTLB
 from m5.objects.ClockedObject import ClockedObject
+from m5.params import *
+from m5.proxy import *
 
 
 class X86PagetableWalker(ClockedObject):

src/arch/x86/kvm/X86KvmCPU.py

@@ -24,12 +24,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-from m5.SimObject import *
-
 from m5.objects.BaseKvmCPU import BaseKvmCPU
 from m5.objects.X86CPU import X86CPU
 from m5.objects.X86MMU import X86MMU
+from m5.params import *
+from m5.SimObject import *
 
 
 class X86KvmCPU(BaseKvmCPU, X86CPU):

src/base/Graphics.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
 from m5.params import *
+from m5.SimObject import SimObject
 
 
 # Image Formats:

src/base/vnc/Vnc.py

@@ -33,9 +33,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.Graphics import *
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class VncInput(SimObject):

src/cpu/BaseCPU.py

@@ -40,20 +40,19 @@
 
 import sys
 
-from m5.SimObject import *
 from m5.defines import buildEnv
-from m5.params import *
-from m5.proxy import *
-from m5.util.fdthelper import *
-
-from m5.objects.ClockedObject import ClockedObject
-from m5.objects.XBar import L2XBar
-from m5.objects.InstTracer import InstTracer
-from m5.objects.CPUTracers import ExeTracer
-from m5.objects.SubSystem import SubSystem
 from m5.objects.ClockDomain import *
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.CPUTracers import ExeTracer
+from m5.objects.InstTracer import InstTracer
 from m5.objects.Platform import Platform
 from m5.objects.ResetPort import ResetResponsePort
+from m5.objects.SubSystem import SubSystem
+from m5.objects.XBar import L2XBar
+from m5.params import *
+from m5.proxy import *
+from m5.SimObject import *
+from m5.util.fdthelper import *
 
 default_tracer = ExeTracer()
 

src/cpu/CPUTracers.py

@@ -24,9 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.InstTracer import InstTracer
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class ExeTracer(InstTracer):

src/cpu/Capstone.py

@@ -33,9 +33,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.InstTracer import InstDisassembler
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class CapstoneDisassembler(InstDisassembler):

src/cpu/CheckerCPU.py

@@ -24,9 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.BaseCPU import BaseCPU
+from m5.params import *
 from m5.SimObject import SimObject
 
 

src/cpu/CpuCluster.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.SubSystem import SubSystem
+from m5.params import *
 
 
 class CpuCluster(SubSystem):

src/cpu/DummyChecker.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.CheckerCPU import CheckerCPU
+from m5.params import *
 
 
 class DummyChecker(CheckerCPU):

src/cpu/FuncUnit.py

@@ -36,8 +36,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
 from m5.params import *
+from m5.SimObject import SimObject
 
 
 class OpClass(Enum):

src/cpu/InstPBTrace.py

@@ -24,10 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
-
 from m5.objects.InstTracer import InstTracer
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class InstPBTrace(InstTracer):

src/cpu/kvm/BaseKvmCPU.py

@@ -33,12 +33,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import *
-from m5.params import *
-from m5.proxy import *
-
 from m5.objects.BaseCPU import BaseCPU
 from m5.objects.KvmVM import KvmVM
+from m5.params import *
+from m5.proxy import *
+from m5.SimObject import *
 
 
 class BaseKvmCPU(BaseCPU):

src/cpu/kvm/KvmVM.py

@@ -35,7 +35,6 @@
 
 from m5.params import *
 from m5.proxy import *
-
 from m5.SimObject import SimObject
 
 

src/cpu/minor/BaseMinorCPU.py

@@ -37,15 +37,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.BranchPredictor import *
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.FuncUnit import OpClass
+from m5.objects.TimingExpr import TimingExpr
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from m5.objects.BaseCPU import BaseCPU
-from m5.objects.DummyChecker import DummyChecker
-from m5.objects.BranchPredictor import *
-from m5.objects.TimingExpr import TimingExpr
-
-from m5.objects.FuncUnit import OpClass
 
 
 class MinorOpClass(SimObject):

src/cpu/o3/BaseO3CPU.py

@@ -37,14 +37,13 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
-from m5.params import *
-from m5.proxy import *
-
 from m5.objects.BaseCPU import BaseCPU
-from m5.objects.FUPool import *
 
 # from m5.objects.O3Checker import O3Checker
 from m5.objects.BranchPredictor import *
+from m5.objects.FUPool import *
+from m5.params import *
+from m5.proxy import *
 
 
 class SMTFetchPolicy(ScopedEnum):

src/cpu/o3/BaseO3Checker.py

@@ -24,8 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.CheckerCPU import CheckerCPU
+from m5.params import *
 
 
 class BaseO3Checker(CheckerCPU):

src/cpu/o3/FUPool.py

@@ -36,10 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.FuncUnit import *
 from m5.objects.FuncUnitConfig import *
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class FUPool(SimObject):

src/cpu/o3/FuncUnitConfig.py

@@ -36,11 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
 from m5.defines import buildEnv
-from m5.params import *
-
 from m5.objects.FuncUnit import *
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class IntALU(FUDesc):

src/cpu/pred/BranchPredictor.py

@@ -37,11 +37,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import *
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-
-from m5.objects.ClockedObject import ClockedObject
+from m5.SimObject import *
 
 
 class BranchType(Enum):

src/cpu/probes/PcCountTracker.py

@@ -24,10 +24,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import SimObject
+from m5.objects.Probe import ProbeListenerObject
 from m5.params import *
 from m5.util.pybind import *
-from m5.objects.Probe import ProbeListenerObject
-from m5.objects import SimObject
 
 
 class PcCountTrackerManager(SimObject):

src/cpu/simple/BaseAtomicSimpleCPU.py

@@ -36,9 +36,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.BaseSimpleCPU import BaseSimpleCPU
 from m5.objects.SimPoint import SimPoint
+from m5.params import *
 
 
 class BaseAtomicSimpleCPU(BaseSimpleCPU):

src/cpu/simple/BaseNonCachingSimpleCPU.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
+from m5.params import *
 
 
 class BaseNonCachingSimpleCPU(BaseAtomicSimpleCPU):

src/cpu/simple/BaseSimpleCPU.py

@@ -25,11 +25,10 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
-from m5.params import *
-
 from m5.objects.BaseCPU import BaseCPU
-from m5.objects.DummyChecker import DummyChecker
 from m5.objects.BranchPredictor import *
+from m5.objects.DummyChecker import DummyChecker
+from m5.params import *
 
 
 class BaseSimpleCPU(BaseCPU):

src/cpu/simple/BaseTimingSimpleCPU.py

@@ -24,9 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.BaseSimpleCPU import BaseSimpleCPU
+from m5.params import *
 
 
 class BaseTimingSimpleCPU(BaseSimpleCPU):

src/cpu/simple/probes/SimPoint.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.Probe import ProbeListenerObject
+from m5.params import *
 
 
 class SimPoint(ProbeListenerObject):

src/cpu/testers/directedtest/RubyDirectedTester.py

@@ -24,11 +24,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-
-from m5.objects.ClockedObject import ClockedObject
+from m5.SimObject import SimObject
 
 
 class DirectedGenerator(SimObject):

src/cpu/testers/gpu_ruby_test/CpuThread.py

@@ -27,11 +27,10 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.TesterThread import TesterThread
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.TesterThread import TesterThread
-
 
 class CpuThread(TesterThread):
     type = "CpuThread"

src/cpu/testers/gpu_ruby_test/DmaThread.py

@@ -27,11 +27,10 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.TesterThread import TesterThread
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.TesterThread import TesterThread
-
 
 class DmaThread(TesterThread):
     type = "DmaThread"

src/cpu/testers/gpu_ruby_test/GpuWavefront.py

@@ -27,11 +27,10 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.TesterThread import TesterThread
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.TesterThread import TesterThread
-
 
 class GpuWavefront(TesterThread):
     type = "GpuWavefront"

src/cpu/testers/memtest/MemTest.py

@@ -36,11 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.ClockedObject import ClockedObject
-
 
 class MemTest(ClockedObject):
     type = "MemTest"

src/cpu/testers/rubytest/RubyTester.py

@@ -25,11 +25,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.ClockedObject import ClockedObject
-
 
 class RubyTester(ClockedObject):
     type = "RubyTester"

src/cpu/testers/traffic_gen/BaseTrafficGen.py

@@ -33,9 +33,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-from m5.objects.ClockedObject import ClockedObject
 
 
 # Types of Stream Generators.

src/cpu/testers/traffic_gen/GUPSGen.py

@@ -25,9 +25,9 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-from m5.objects.ClockedObject import ClockedObject
 
 
 class GUPSGen(ClockedObject):

src/cpu/testers/traffic_gen/PyTrafficGen.py

@@ -34,9 +34,8 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
-from m5.SimObject import *
-
 from m5.objects.BaseTrafficGen import *
+from m5.SimObject import *
 
 
 class PyTrafficGen(BaseTrafficGen):

src/cpu/testers/traffic_gen/TrafficGen.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.BaseTrafficGen import *
+from m5.params import *
 
 
 # The behaviour of this traffic generator is specified in a

src/cpu/trace/TraceCPU.py

@@ -33,9 +33,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-from m5.objects.ClockedObject import ClockedObject
 
 
 class TraceCPU(ClockedObject):

src/dev/BadDevice.py

@@ -24,8 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.Device import BasicPioDevice
+from m5.params import *
 
 
 class BadDevice(BasicPioDevice):

src/dev/Device.py

@@ -36,12 +36,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
 from m5.util.fdthelper import *
 
-from m5.objects.ClockedObject import ClockedObject
-
 
 class PioDevice(ClockedObject):
     type = "PioDevice"

src/dev/IntPin.py

@@ -23,7 +23,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import Port, VectorPort
+from m5.params import (
+    Port,
+    VectorPort,
+)
 
 INT_SOURCE_ROLE = "Int Source Pin"
 INT_SINK_ROLE = "Int Sink Pin"

src/dev/Platform.py

@@ -24,9 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
+from m5.SimObject import SimObject
 
 
 class Platform(SimObject):

src/dev/ResetPort.py

@@ -23,7 +23,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import Port, VectorPort
+from m5.params import (
+    Port,
+    VectorPort,
+)
 
 RESET_REQUEST_ROLE = "Reset Request"
 RESET_RESPONSE_ROLE = "Reset Response"

src/dev/amdgpu/AMDGPU.py

@@ -27,12 +27,19 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.Device import (
+    DmaDevice,
+    DmaVirtDevice,
+)
+from m5.objects.PciDevice import (
+    PciDevice,
+    PciLegacyIoBar,
+    PciMemBar,
+    PciMemUpperBar,
+)
 from m5.params import *
 from m5.proxy import *
-from m5.objects.PciDevice import PciDevice
-from m5.objects.PciDevice import PciMemBar, PciMemUpperBar, PciLegacyIoBar
-from m5.objects.Device import DmaDevice, DmaVirtDevice
-from m5.objects.ClockedObject import ClockedObject
 
 
 # PCI device model for an AMD Vega 10 based GPU. The PCI codes and BARs