d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
81 lines
3.2 KiB
Python
81 lines
3.2 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.BaseCPU import BaseCPU
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from m5.objects.KvmVM import KvmVM
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from m5.params import *
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from m5.proxy import *
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from m5.SimObject import *
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class BaseKvmCPU(BaseCPU):
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type = "BaseKvmCPU"
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cxx_header = "cpu/kvm/base.hh"
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cxx_class = "gem5::BaseKvmCPU"
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abstract = True
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@cxxMethod
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def dump(self):
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"""Dump the internal state of KVM to standard out."""
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pass
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@classmethod
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def memory_mode(cls):
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return "atomic_noncaching"
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@classmethod
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def require_caches(cls):
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return False
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@classmethod
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def support_take_over(cls):
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return True
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usePerf = Param.Bool(
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True,
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"Use perf for gathering statistics from the guest and providing "
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"statistic-related functionalities",
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)
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useCoalescedMMIO = Param.Bool(False, "Use coalesced MMIO (EXPERIMENTAL)")
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usePerfOverflow = Param.Bool(
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False, "Use perf event overflow counters (EXPERIMENTAL)"
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)
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alwaysSyncTC = Param.Bool(
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False, "Always sync thread contexts on entry/exit"
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)
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hostFreq = Param.Clock("2GHz", "Host clock frequency")
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hostFactor = Param.Float(1.0, "Cycle scale factor")
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