d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
125 lines
4.1 KiB
Python
125 lines
4.1 KiB
Python
# Copyright 2019 Google, Inc.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.SystemC import SystemC_ScModule
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from m5.objects.Tlm import (
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TlmInitiatorSocket,
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TlmTargetSocket,
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)
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from m5.params import *
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from m5.proxy import *
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def AMBA_TARGET_ROLE(width):
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return "AMBA TARGET %d" % width
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def AMBA_INITIATOR_ROLE(width):
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return "AMBA INITIATOR %d" % width
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def SC_REQUEST_PORT_ROLE(port_type):
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return f"SC REQUEST PORT for {port_type}"
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def SC_RESPONSE_PORT_ROLE(port_type):
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return f"SC RESPONSE PORT for {port_type}"
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class AmbaTargetSocket(Port):
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def __init__(self, width, desc):
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my_role = AMBA_INITIATOR_ROLE(width)
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peer_role = AMBA_TARGET_ROLE(width)
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Port.compat(my_role, peer_role)
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super().__init__(my_role, desc)
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class VectorAmbaTargetSocket(VectorPort):
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def __init__(self, width, desc):
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my_role = AMBA_INITIATOR_ROLE(width)
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peer_role = AMBA_TARGET_ROLE(width)
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Port.compat(my_role, peer_role)
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super().__init__(my_role, desc)
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class AmbaInitiatorSocket(Port):
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def __init__(self, width, desc):
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my_role = AMBA_TARGET_ROLE(width)
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peer_role = AMBA_INITIATOR_ROLE(width)
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Port.compat(my_role, peer_role)
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super().__init__(my_role, desc, is_source=True)
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class VectorAmbaInitiatorSocket(VectorPort):
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def __init__(self, width, desc):
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my_role = AMBA_TARGET_ROLE(width)
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peer_role = AMBA_INITIATOR_ROLE(width)
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Port.compat(my_role, peer_role)
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super().__init__(my_role, desc, is_source=True)
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class ScRequestPort(Port):
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def __init__(self, desc, port_type):
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my_role = SC_REQUEST_PORT_ROLE(port_type)
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peer_role = SC_RESPONSE_PORT_ROLE(port_type)
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Port.compat(my_role, peer_role)
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super().__init__(my_role, desc)
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class ScResponsePort(Port):
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def __init__(self, desc, port_type):
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my_role = SC_RESPONSE_PORT_ROLE(port_type)
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peer_role = SC_REQUEST_PORT_ROLE(port_type)
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Port.compat(my_role, peer_role)
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super().__init__(my_role, desc)
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class AmbaToTlmBridge64(SystemC_ScModule):
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type = "AmbaToTlmBridge64"
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cxx_class = "gem5::fastmodel::AmbaToTlmBridge64"
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cxx_header = "arch/arm/fastmodel/amba_to_tlm_bridge.hh"
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amba = AmbaTargetSocket(64, "AMBA PV target socket")
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tlm = TlmInitiatorSocket(64, "TLM initiator socket")
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set_stream_id = Param.Bool(
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False, "Set this true to forward stream ID to gem5 world"
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)
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class AmbaFromTlmBridge64(SystemC_ScModule):
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type = "AmbaFromTlmBridge64"
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cxx_class = "gem5::fastmodel::AmbaFromTlmBridge64"
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cxx_header = "arch/arm/fastmodel/amba_from_tlm_bridge.hh"
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tlm = TlmTargetSocket(64, "TLM target socket")
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amba = AmbaInitiatorSocket(64, "AMBA PV initiator socket")
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