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arch: Template the generic PC types on the instruction width.

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These had been templated on a type, and then the width of that type was
considered the amount the PC should advance when executing straight line
code. That type was MachInst, which was loosely the size of an
instruction, but was practically whatever sized data type was fed into
the decoder at a time.

Instead of tying this to a type, this change moves it over to be a
simple number. This avoids a level of indirection, and also further
decouples the type the decoder might use as input from the instruction
size.

Change-Id: I797876a33d27e759c7a6e23a658179201fabfa47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40176
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Gabe Black
2021-01-29 21:16:25 -08:00
parent e555fedf96
commit d583a9a227
8 changed files with 42 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/arm/types.hh
View File

@@ -213,11 +213,11 @@ namespace ArmISA
Bitfield<11, 8> ltcoproc;
EndBitUnion(ExtMachInst)
class PCState : public GenericISA::UPCState<MachInst>
class PCState : public GenericISA::UPCState<4>
{
protected:
typedef GenericISA::UPCState<MachInst> Base;
typedef GenericISA::UPCState<4> Base;
enum FlagBits
{

66
src/arch/generic/types.hh
View File

@@ -137,7 +137,7 @@ class PCStateBase : public Serializable
*/
// The most basic type of PC.
template <class MachInst>
template <int InstWidth>
class SimplePCState : public PCStateBase
{
protected:
@@ -155,7 +155,7 @@ class SimplePCState : public PCStateBase
set(Addr val)
{
pc(val);
npc(val + sizeof(MachInst));
npc(val + InstWidth);
};
void
@@ -170,7 +170,7 @@ class SimplePCState : public PCStateBase
bool
branching() const
{
return this->npc() != this->pc() + sizeof(MachInst);
return this->npc() != this->pc() + InstWidth;
}
// Advance the PC.
@@ -178,24 +178,24 @@ class SimplePCState : public PCStateBase
advance()
{
_pc = _npc;
_npc += sizeof(MachInst);
_npc += InstWidth;
}
};
template <class MachInst>
template <int InstWidth>
std::ostream &
operator<<(std::ostream & os, const SimplePCState<MachInst> &pc)
operator<<(std::ostream & os, const SimplePCState<InstWidth> &pc)
{
ccprintf(os, "(%#x=>%#x)", pc.pc(), pc.npc());
return os;
}
// A PC and microcode PC.
template <class MachInst>
class UPCState : public SimplePCState<MachInst>
template <int InstWidth>
class UPCState : public SimplePCState<InstWidth>
{
protected:
typedef SimplePCState<MachInst> Base;
typedef SimplePCState<InstWidth> Base;
MicroPC _upc;
MicroPC _nupc;
@@ -228,7 +228,7 @@ class UPCState : public SimplePCState<MachInst>
bool
branching() const
{
return this->npc() != this->pc() + sizeof(MachInst) ||
return this->npc() != this->pc() + InstWidth ||
this->nupc() != this->upc() + 1;
}
@@ -258,7 +258,7 @@ class UPCState : public SimplePCState<MachInst>
}
bool
operator == (const UPCState<MachInst> &opc) const
operator == (const UPCState<InstWidth> &opc) const
{
return Base::_pc == opc._pc &&
Base::_npc == opc._npc &&
@@ -266,7 +266,7 @@ class UPCState : public SimplePCState<MachInst>
}
bool
operator != (const UPCState<MachInst> &opc) const
operator != (const UPCState<InstWidth> &opc) const
{
return !(*this == opc);
}
@@ -288,9 +288,9 @@ class UPCState : public SimplePCState<MachInst>
}
};
template <class MachInst>
template <int InstWidth>
std::ostream &
operator<<(std::ostream & os, const UPCState<MachInst> &pc)
operator<<(std::ostream & os, const UPCState<InstWidth> &pc)
{
ccprintf(os, "(%#x=>%#x).(%d=>%d)",
pc.pc(), pc.npc(), pc.upc(), pc.nupc());
@@ -298,11 +298,11 @@ operator<<(std::ostream & os, const UPCState<MachInst> &pc)
}
// A PC with a delay slot.
template <class MachInst>
class DelaySlotPCState : public SimplePCState<MachInst>
template <int InstWidth>
class DelaySlotPCState : public SimplePCState<InstWidth>
{
protected:
typedef SimplePCState<MachInst> Base;
typedef SimplePCState<InstWidth> Base;
Addr _nnpc;
@@ -315,7 +315,7 @@ class DelaySlotPCState : public SimplePCState<MachInst>
set(Addr val)
{
Base::set(val);
nnpc(val + 2 * sizeof(MachInst));
nnpc(val + 2 * InstWidth);
}
DelaySlotPCState() {}
@@ -324,9 +324,9 @@ class DelaySlotPCState : public SimplePCState<MachInst>
bool
branching() const
{
return !(this->nnpc() == this->npc() + sizeof(MachInst) &&
(this->npc() == this->pc() + sizeof(MachInst) ||
this->npc() == this->pc() + 2 * sizeof(MachInst)));
return !(this->nnpc() == this->npc() + InstWidth &&
(this->npc() == this->pc() + InstWidth ||
this->npc() == this->pc() + 2 * InstWidth));
}
// Advance the PC.
@@ -335,11 +335,11 @@ class DelaySlotPCState : public SimplePCState<MachInst>
{
Base::_pc = Base::_npc;
Base::_npc = _nnpc;
_nnpc += sizeof(MachInst);
_nnpc += InstWidth;
}
bool
operator == (const DelaySlotPCState<MachInst> &opc) const
operator == (const DelaySlotPCState<InstWidth> &opc) const
{
return Base::_pc == opc._pc &&
Base::_npc == opc._npc &&
@@ -347,7 +347,7 @@ class DelaySlotPCState : public SimplePCState<MachInst>
}
bool
operator != (const DelaySlotPCState<MachInst> &opc) const
operator != (const DelaySlotPCState<InstWidth> &opc) const
{
return !(*this == opc);
}
@@ -367,9 +367,9 @@ class DelaySlotPCState : public SimplePCState<MachInst>
}
};
template <class MachInst>
template <int InstWidth>
std::ostream &
operator<<(std::ostream & os, const DelaySlotPCState<MachInst> &pc)
operator<<(std::ostream & os, const DelaySlotPCState<InstWidth> &pc)
{
ccprintf(os, "(%#x=>%#x=>%#x)",
pc.pc(), pc.npc(), pc.nnpc());
@@ -377,11 +377,11 @@ operator<<(std::ostream & os, const DelaySlotPCState<MachInst> &pc)
}
// A PC with a delay slot and a microcode PC.
template <class MachInst>
class DelaySlotUPCState : public DelaySlotPCState<MachInst>
template <int InstWidth>
class DelaySlotUPCState : public DelaySlotPCState<InstWidth>
{
protected:
typedef DelaySlotPCState<MachInst> Base;
typedef DelaySlotPCState<InstWidth> Base;
MicroPC _upc;
MicroPC _nupc;
@@ -435,7 +435,7 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
}
bool
operator == (const DelaySlotUPCState<MachInst> &opc) const
operator == (const DelaySlotUPCState<InstWidth> &opc) const
{
return Base::_pc == opc._pc &&
Base::_npc == opc._npc &&
@@ -444,7 +444,7 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
}
bool
operator != (const DelaySlotUPCState<MachInst> &opc) const
operator != (const DelaySlotUPCState<InstWidth> &opc) const
{
return !(*this == opc);
}
@@ -466,9 +466,9 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
}
};
template <class MachInst>
template <int InstWidth>
std::ostream &
operator<<(std::ostream & os, const DelaySlotUPCState<MachInst> &pc)
operator<<(std::ostream & os, const DelaySlotUPCState<InstWidth> &pc)
{
ccprintf(os, "(%#x=>%#x=>%#x).(%d=>%d)",
pc.pc(), pc.npc(), pc.nnpc(), pc.upc(), pc.nupc());

2
src/arch/mips/types.hh
View File

@@ -38,7 +38,7 @@ namespace MipsISA
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
typedef GenericISA::DelaySlotPCState<MachInst> PCState;
typedef GenericISA::DelaySlotPCState<4> PCState;
//used in FP convert & round function
enum ConvertType

8
src/arch/null/types.hh
View File

@@ -42,14 +42,8 @@
namespace NullISA
{
typedef uint32_t MachInst;
class PCState : public GenericISA::UPCState<MachInst>
{
protected:
typedef GenericISA::UPCState<MachInst> Base;
};
typedef GenericISA::UPCState<4> PCState;
}

2
src/arch/power/types.hh
View File

@@ -81,7 +81,7 @@ BitUnion32(ExtMachInst)
Bitfield<19, 12> fxm;
EndBitUnion(ExtMachInst)
typedef GenericISA::SimplePCState<MachInst> PCState;
typedef GenericISA::SimplePCState<4> PCState;
// typedef uint64_t LargestRead;
// // Need to use 64 bits to make sure that read requests get handled properly

2
src/arch/riscv/types.hh
View File

@@ -50,7 +50,7 @@ namespace RiscvISA
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
class PCState : public GenericISA::UPCState<MachInst>
class PCState : public GenericISA::UPCState<4>
{
private:
bool _compressed;

2
src/arch/sparc/types.hh
View File

@@ -38,7 +38,7 @@ namespace SparcISA
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
typedef GenericISA::DelaySlotUPCState<4> PCState;
}

4
src/arch/x86/types.hh
View File

@@ -287,10 +287,10 @@ operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
return true;
}
class PCState : public GenericISA::UPCState<MachInst>
class PCState : public GenericISA::UPCState<8>
{
protected:
typedef GenericISA::UPCState<MachInst> Base;
typedef GenericISA::UPCState<8> Base;
uint8_t _size;