diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 2ec5255add..6d5bc2a908 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -213,11 +213,11 @@ namespace ArmISA
         Bitfield<11, 8>  ltcoproc;
     EndBitUnion(ExtMachInst)
 
-    class PCState : public GenericISA::UPCState<MachInst>
+    class PCState : public GenericISA::UPCState<4>
     {
       protected:
 
-        typedef GenericISA::UPCState<MachInst> Base;
+        typedef GenericISA::UPCState<4> Base;
 
         enum FlagBits
         {
diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index 0f1e83737c..2e3b8471d8 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -137,7 +137,7 @@ class PCStateBase : public Serializable
  */
 
 // The most basic type of PC.
-template <class MachInst>
+template <int InstWidth>
 class SimplePCState : public PCStateBase
 {
   protected:
@@ -155,7 +155,7 @@ class SimplePCState : public PCStateBase
     set(Addr val)
     {
         pc(val);
-        npc(val + sizeof(MachInst));
+        npc(val + InstWidth);
     };
 
     void
@@ -170,7 +170,7 @@ class SimplePCState : public PCStateBase
     bool
     branching() const
     {
-        return this->npc() != this->pc() + sizeof(MachInst);
+        return this->npc() != this->pc() + InstWidth;
     }
 
     // Advance the PC.
@@ -178,24 +178,24 @@ class SimplePCState : public PCStateBase
     advance()
     {
         _pc = _npc;
-        _npc += sizeof(MachInst);
+        _npc += InstWidth;
     }
 };
 
-template <class MachInst>
+template <int InstWidth>
 std::ostream &
-operator<<(std::ostream & os, const SimplePCState<MachInst> &pc)
+operator<<(std::ostream & os, const SimplePCState<InstWidth> &pc)
 {
     ccprintf(os, "(%#x=>%#x)", pc.pc(), pc.npc());
     return os;
 }
 
 // A PC and microcode PC.
-template <class MachInst>
-class UPCState : public SimplePCState<MachInst>
+template <int InstWidth>
+class UPCState : public SimplePCState<InstWidth>
 {
   protected:
-    typedef SimplePCState<MachInst> Base;
+    typedef SimplePCState<InstWidth> Base;
 
     MicroPC _upc;
     MicroPC _nupc;
@@ -228,7 +228,7 @@ class UPCState : public SimplePCState<MachInst>
     bool
     branching() const
     {
-        return this->npc() != this->pc() + sizeof(MachInst) ||
+        return this->npc() != this->pc() + InstWidth ||
                this->nupc() != this->upc() + 1;
     }
 
@@ -258,7 +258,7 @@ class UPCState : public SimplePCState<MachInst>
     }
 
     bool
-    operator == (const UPCState<MachInst> &opc) const
+    operator == (const UPCState<InstWidth> &opc) const
     {
         return Base::_pc == opc._pc &&
                Base::_npc == opc._npc &&
@@ -266,7 +266,7 @@ class UPCState : public SimplePCState<MachInst>
     }
 
     bool
-    operator != (const UPCState<MachInst> &opc) const
+    operator != (const UPCState<InstWidth> &opc) const
     {
         return !(*this == opc);
     }
@@ -288,9 +288,9 @@ class UPCState : public SimplePCState<MachInst>
     }
 };
 
-template <class MachInst>
+template <int InstWidth>
 std::ostream &
-operator<<(std::ostream & os, const UPCState<MachInst> &pc)
+operator<<(std::ostream & os, const UPCState<InstWidth> &pc)
 {
     ccprintf(os, "(%#x=>%#x).(%d=>%d)",
             pc.pc(), pc.npc(), pc.upc(), pc.nupc());
@@ -298,11 +298,11 @@ operator<<(std::ostream & os, const UPCState<MachInst> &pc)
 }
 
 // A PC with a delay slot.
-template <class MachInst>
-class DelaySlotPCState : public SimplePCState<MachInst>
+template <int InstWidth>
+class DelaySlotPCState : public SimplePCState<InstWidth>
 {
   protected:
-    typedef SimplePCState<MachInst> Base;
+    typedef SimplePCState<InstWidth> Base;
 
     Addr _nnpc;
 
@@ -315,7 +315,7 @@ class DelaySlotPCState : public SimplePCState<MachInst>
     set(Addr val)
     {
         Base::set(val);
-        nnpc(val + 2 * sizeof(MachInst));
+        nnpc(val + 2 * InstWidth);
     }
 
     DelaySlotPCState() {}
@@ -324,9 +324,9 @@ class DelaySlotPCState : public SimplePCState<MachInst>
     bool
     branching() const
     {
-        return !(this->nnpc() == this->npc() + sizeof(MachInst) &&
-                 (this->npc() == this->pc() + sizeof(MachInst) ||
-                  this->npc() == this->pc() + 2 * sizeof(MachInst)));
+        return !(this->nnpc() == this->npc() + InstWidth &&
+                 (this->npc() == this->pc() + InstWidth ||
+                  this->npc() == this->pc() + 2 * InstWidth));
     }
 
     // Advance the PC.
@@ -335,11 +335,11 @@ class DelaySlotPCState : public SimplePCState<MachInst>
     {
         Base::_pc = Base::_npc;
         Base::_npc = _nnpc;
-        _nnpc += sizeof(MachInst);
+        _nnpc += InstWidth;
     }
 
     bool
-    operator == (const DelaySlotPCState<MachInst> &opc) const
+    operator == (const DelaySlotPCState<InstWidth> &opc) const
     {
         return Base::_pc == opc._pc &&
                Base::_npc == opc._npc &&
@@ -347,7 +347,7 @@ class DelaySlotPCState : public SimplePCState<MachInst>
     }
 
     bool
-    operator != (const DelaySlotPCState<MachInst> &opc) const
+    operator != (const DelaySlotPCState<InstWidth> &opc) const
     {
         return !(*this == opc);
     }
@@ -367,9 +367,9 @@ class DelaySlotPCState : public SimplePCState<MachInst>
     }
 };
 
-template <class MachInst>
+template <int InstWidth>
 std::ostream &
-operator<<(std::ostream & os, const DelaySlotPCState<MachInst> &pc)
+operator<<(std::ostream & os, const DelaySlotPCState<InstWidth> &pc)
 {
     ccprintf(os, "(%#x=>%#x=>%#x)",
             pc.pc(), pc.npc(), pc.nnpc());
@@ -377,11 +377,11 @@ operator<<(std::ostream & os, const DelaySlotPCState<MachInst> &pc)
 }
 
 // A PC with a delay slot and a microcode PC.
-template <class MachInst>
-class DelaySlotUPCState : public DelaySlotPCState<MachInst>
+template <int InstWidth>
+class DelaySlotUPCState : public DelaySlotPCState<InstWidth>
 {
   protected:
-    typedef DelaySlotPCState<MachInst> Base;
+    typedef DelaySlotPCState<InstWidth> Base;
 
     MicroPC _upc;
     MicroPC _nupc;
@@ -435,7 +435,7 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
     }
 
     bool
-    operator == (const DelaySlotUPCState<MachInst> &opc) const
+    operator == (const DelaySlotUPCState<InstWidth> &opc) const
     {
         return Base::_pc == opc._pc &&
                Base::_npc == opc._npc &&
@@ -444,7 +444,7 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
     }
 
     bool
-    operator != (const DelaySlotUPCState<MachInst> &opc) const
+    operator != (const DelaySlotUPCState<InstWidth> &opc) const
     {
         return !(*this == opc);
     }
@@ -466,9 +466,9 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
     }
 };
 
-template <class MachInst>
+template <int InstWidth>
 std::ostream &
-operator<<(std::ostream & os, const DelaySlotUPCState<MachInst> &pc)
+operator<<(std::ostream & os, const DelaySlotUPCState<InstWidth> &pc)
 {
     ccprintf(os, "(%#x=>%#x=>%#x).(%d=>%d)",
             pc.pc(), pc.npc(), pc.nnpc(), pc.upc(), pc.nupc());
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index 9168363e76..33a3afc0da 100644
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -38,7 +38,7 @@ namespace MipsISA
 typedef uint32_t MachInst;
 typedef uint64_t ExtMachInst;
 
-typedef GenericISA::DelaySlotPCState<MachInst> PCState;
+typedef GenericISA::DelaySlotPCState<4> PCState;
 
 //used in FP convert & round function
 enum ConvertType
diff --git a/src/arch/null/types.hh b/src/arch/null/types.hh
index 3fa7479bfa..9a8295eaa5 100644
--- a/src/arch/null/types.hh
+++ b/src/arch/null/types.hh
@@ -42,14 +42,8 @@
 
 namespace NullISA
 {
-    typedef uint32_t MachInst;
 
-    class PCState : public GenericISA::UPCState<MachInst>
-    {
-      protected:
-
-        typedef GenericISA::UPCState<MachInst> Base;
-    };
+typedef GenericISA::UPCState<4> PCState;
 
 }
 
diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index 1e896e42c0..cd060ccc1c 100644
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -81,7 +81,7 @@ BitUnion32(ExtMachInst)
     Bitfield<19, 12> fxm;
 EndBitUnion(ExtMachInst)
 
-typedef GenericISA::SimplePCState<MachInst> PCState;
+typedef GenericISA::SimplePCState<4> PCState;
 
 // typedef uint64_t LargestRead;
 // // Need to use 64 bits to make sure that read requests get handled properly
diff --git a/src/arch/riscv/types.hh b/src/arch/riscv/types.hh
index 38923b8f29..68c3f98762 100644
--- a/src/arch/riscv/types.hh
+++ b/src/arch/riscv/types.hh
@@ -50,7 +50,7 @@ namespace RiscvISA
 typedef uint32_t MachInst;
 typedef uint64_t ExtMachInst;
 
-class PCState : public GenericISA::UPCState<MachInst>
+class PCState : public GenericISA::UPCState<4>
 {
   private:
     bool _compressed;
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
index 885bdc992e..ffb9806690 100644
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -38,7 +38,7 @@ namespace SparcISA
 typedef uint32_t MachInst;
 typedef uint64_t ExtMachInst;
 
-typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
+typedef GenericISA::DelaySlotUPCState<4> PCState;
 
 }
 
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 422cada0b5..f2b612f91d 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -287,10 +287,10 @@ operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
     return true;
 }
 
-class PCState : public GenericISA::UPCState<MachInst>
+class PCState : public GenericISA::UPCState<8>
 {
   protected:
-    typedef GenericISA::UPCState<MachInst> Base;
+    typedef GenericISA::UPCState<8> Base;
 
     uint8_t _size;