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arch-arm: Check ELIs64 for EL2 when in EL2&0 regime

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The problem with:

ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL);

Is that when we are executing at EL0 in host (EL2&0 translation
regime), the execution mode (AArch32 vs AArch64) is dictated
by EL2 and not by EL1 (which is the guest)

Change-Id: I463a2a9461c94d0886990ae3d0a6e22aeb4b9ea3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-01-03 16:54:54 +00:00
parent 458c98082c
commit d42ef792bf
4 changed files with 23 additions and 6 deletions
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4
src/arch/arm/mmu.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013, 2016-2023 Arm Limited
* Copyright (c) 2010-2013, 2016-2024 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1202,7 +1202,7 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
currRegime = translationRegime(tc, aarch64EL);
aarch64 = isStage2 ?
ELIs64(tc, EL2) :
ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL);
ELIs64(tc, translationEl(currRegime));
if (aarch64) { // AArch64
// determine EL we need to translate in

4
src/arch/arm/table_walker.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2019, 2021-2023 Arm Limited
* Copyright (c) 2010, 2012-2019, 2021-2024 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -347,7 +347,7 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid,
currState->regime =
translationRegime(_tc, currState->el);
currState->aarch64 =
ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el);
ELIs64(_tc, translationEl(currState->regime));
}
currState->transState = _trans;
currState->req = _req;

18
src/arch/arm/utility.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2009-2014, 2016-2020, 2022-2023 Arm Limited
* Copyright (c) 2009-2014, 2016-2020, 2022-2024 Arm Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -1385,5 +1385,21 @@ translationRegime(ThreadContext *tc, ExceptionLevel el)
}
}
ExceptionLevel
translationEl(TranslationRegime regime)
{
switch (regime) {
case TranslationRegime::EL10:
return EL1;
case TranslationRegime::EL20:
case TranslationRegime::EL2:
return EL2;
case TranslationRegime::EL3:
return EL3;
default:
return EL1;
}
}
} // namespace ArmISA
} // namespace gem5

3
src/arch/arm/utility.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2013, 2016-2020, 2022-2023 Arm Limited
* Copyright (c) 2010, 2012-2013, 2016-2020, 2022-2024 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -368,6 +368,7 @@ bool fgtEnabled(ThreadContext *tc);
bool isHcrxEL2Enabled(ThreadContext *tc);
TranslationRegime translationRegime(ThreadContext *tc, ExceptionLevel el);
ExceptionLevel translationEl(TranslationRegime regime);
static inline bool
useVMID(TranslationRegime regime)