diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc
index 2df2d9f932..dc50b13358 100644
--- a/src/arch/arm/mmu.cc
+++ b/src/arch/arm/mmu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2016-2023 Arm Limited
+ * Copyright (c) 2010-2013, 2016-2024 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1202,7 +1202,7 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
     currRegime = translationRegime(tc, aarch64EL);
     aarch64 = isStage2 ?
         ELIs64(tc, EL2) :
-        ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL);
+        ELIs64(tc, translationEl(currRegime));
 
     if (aarch64) {  // AArch64
         // determine EL we need to translate in
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index fa95e529c9..4ae18b3b83 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2019, 2021-2023 Arm Limited
+ * Copyright (c) 2010, 2012-2019, 2021-2024 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -347,7 +347,7 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid,
         currState->regime =
             translationRegime(_tc, currState->el);
         currState->aarch64 =
-            ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el);
+            ELIs64(_tc, translationEl(currState->regime));
     }
     currState->transState = _trans;
     currState->req = _req;
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 6966f15934..ffeca272c2 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2014, 2016-2020, 2022-2023 Arm Limited
+ * Copyright (c) 2009-2014, 2016-2020, 2022-2024 Arm Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -1385,5 +1385,21 @@ translationRegime(ThreadContext *tc, ExceptionLevel el)
     }
 }
 
+ExceptionLevel
+translationEl(TranslationRegime regime)
+{
+    switch (regime) {
+      case TranslationRegime::EL10:
+        return EL1;
+      case TranslationRegime::EL20:
+      case TranslationRegime::EL2:
+        return EL2;
+      case TranslationRegime::EL3:
+        return EL3;
+      default:
+        return EL1;
+    }
+}
+
 } // namespace ArmISA
 } // namespace gem5
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index a1464e6a63..8bbb87a58c 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2016-2020, 2022-2023 Arm Limited
+ * Copyright (c) 2010, 2012-2013, 2016-2020, 2022-2024 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -368,6 +368,7 @@ bool fgtEnabled(ThreadContext *tc);
 bool isHcrxEL2Enabled(ThreadContext *tc);
 
 TranslationRegime translationRegime(ThreadContext *tc, ExceptionLevel el);
+ExceptionLevel translationEl(TranslationRegime regime);
 
 static inline bool
 useVMID(TranslationRegime regime)