misc: pass ThreadContext on ISA clear

This patch changes the clear API for the ISAs to pass the ThreadContext
issuing the call. This allows the ISA to carry out maintainance
operations on the TC state.

Change-Id: I40d6cf39c321521a221146aa0fd8f2cf665d39c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25465
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/isa.hh

@@ -463,9 +463,10 @@ namespace ArmISA
         }
 
       public:
-        void clear();
+        void clear(ThreadContext *tc) { clear(); }
 
       protected:
+        void clear();
         void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
         void clear64(const ArmISAParams *p);
         void initID32(const ArmISAParams *p);

src/arch/mips/isa.hh

@@ -72,8 +72,12 @@ namespace MipsISA
         std::vector<BankType> bankType;
 
       public:
+        void clear(ThreadContext *tc) { clear(); }
+
+      protected:
         void clear();
 
+      public:
         void configCP();
 
         unsigned getVPENum(ThreadID tid) const;

src/arch/power/isa.hh

@@ -54,11 +54,19 @@ class ISA : public BaseISA
   public:
     typedef PowerISAParams Params;
 
+    void
+    clear(ThreadContext *tc)
+    {
+        clear();
+    }
+
+  protected:
     void
     clear()
     {
     }
 
+  public:
     RegVal
     readMiscRegNoEffect(int misc_reg) const
     {

src/arch/riscv/isa.hh

@@ -68,8 +68,12 @@ class ISA : public BaseISA
   public:
     typedef RiscvISAParams Params;
 
+    void clear(ThreadContext *tc) { clear(); }
+
+  protected:
     void clear();
 
+  public:
     RegVal readMiscRegNoEffect(int misc_reg) const;
     RegVal readMiscReg(int misc_reg, ThreadContext *tc);
     void setMiscRegNoEffect(int misc_reg, RegVal val);

src/arch/sparc/isa.hh

@@ -165,7 +165,7 @@ class ISA : public BaseISA
 
   public:
 
-    void clear();
+    void clear(ThreadContext *tc) { clear(); }
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;
@@ -176,6 +176,7 @@ class ISA : public BaseISA
     using BaseISA::startup;
 
   protected:
+    void clear();
     bool isHyperPriv() { return hpstate.hpriv; }
     bool isPriv() { return hpstate.hpriv || pstate.priv; }
     bool isNonPriv() { return !isPriv(); }

src/arch/x86/isa.hh

@@ -54,11 +54,12 @@ namespace X86ISA
         void updateHandyM5Reg(Efer efer, CR0 cr0,
                 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
                 ThreadContext *tc);
+        void clear();
 
       public:
         typedef X86ISAParams Params;
 
-        void clear();
+        void clear(ThreadContext *tc) { clear(); }
 
         ISA(Params *p);
         const Params *params() const;

src/cpu/o3/thread_context_impl.hh

@@ -197,7 +197,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::clearArchRegs()
 {
-    cpu->isa[thread->threadId()]->clear();
+    cpu->isa[thread->threadId()]->clear(this);
 }
 
 template <class Impl>

src/cpu/simple_thread.hh

@@ -296,7 +296,7 @@ class SimpleThread : public ThreadState, public ThreadContext
         for (auto &pred_reg: vecPredRegs)
             pred_reg.reset();
         ccRegs.fill(0);
-        isa->clear();
+        isa->clear(this);
     }
 
     //