diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 14ccb5cb87..89be0158ac 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -463,9 +463,10 @@ namespace ArmISA
         }
 
       public:
-        void clear();
+        void clear(ThreadContext *tc) { clear(); }
 
       protected:
+        void clear();
         void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
         void clear64(const ArmISAParams *p);
         void initID32(const ArmISAParams *p);
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 0f5f6af7d6..73cb0462ac 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -72,8 +72,12 @@ namespace MipsISA
         std::vector<BankType> bankType;
 
       public:
+        void clear(ThreadContext *tc) { clear(); }
+
+      protected:
         void clear();
 
+      public:
         void configCP();
 
         unsigned getVPENum(ThreadID tid) const;
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index fb6c2da43b..c82b7bb412 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -54,11 +54,19 @@ class ISA : public BaseISA
   public:
     typedef PowerISAParams Params;
 
+    void
+    clear(ThreadContext *tc)
+    {
+        clear();
+    }
+
+  protected:
     void
     clear()
     {
     }
 
+  public:
     RegVal
     readMiscRegNoEffect(int misc_reg) const
     {
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 227b812333..4bf0fdb058 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -68,8 +68,12 @@ class ISA : public BaseISA
   public:
     typedef RiscvISAParams Params;
 
+    void clear(ThreadContext *tc) { clear(); }
+
+  protected:
     void clear();
 
+  public:
     RegVal readMiscRegNoEffect(int misc_reg) const;
     RegVal readMiscReg(int misc_reg, ThreadContext *tc);
     void setMiscRegNoEffect(int misc_reg, RegVal val);
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 0e67fbb938..63eab2e2c0 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -165,7 +165,7 @@ class ISA : public BaseISA
 
   public:
 
-    void clear();
+    void clear(ThreadContext *tc) { clear(); }
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;
@@ -176,6 +176,7 @@ class ISA : public BaseISA
     using BaseISA::startup;
 
   protected:
+    void clear();
     bool isHyperPriv() { return hpstate.hpriv; }
     bool isPriv() { return hpstate.hpriv || pstate.priv; }
     bool isNonPriv() { return !isPriv(); }
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index e801dea0e5..774321ac35 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -54,11 +54,12 @@ namespace X86ISA
         void updateHandyM5Reg(Efer efer, CR0 cr0,
                 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
                 ThreadContext *tc);
+        void clear();
 
       public:
         typedef X86ISAParams Params;
 
-        void clear();
+        void clear(ThreadContext *tc) { clear(); }
 
         ISA(Params *p);
         const Params *params() const;
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 5e0b1767b8..104e63cab9 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -197,7 +197,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::clearArchRegs()
 {
-    cpu->isa[thread->threadId()]->clear();
+    cpu->isa[thread->threadId()]->clear(this);
 }
 
 template <class Impl>
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 89bb3d96eb..d63bf0bf98 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -296,7 +296,7 @@ class SimpleThread : public ThreadState, public ThreadContext
         for (auto &pred_reg: vecPredRegs)
             pred_reg.reset();
         ccRegs.fill(0);
-        isa->clear();
+        isa->clear(this);
     }
 
     //