arch,cpu: Move getExecutingAsid to the ISA class.

This function was switched based on the ISA, and returned 0 on
everything except SPARC and ARM. It was used only when tracing
instruction execution with --debug-flags=Exec.

Change-Id: I70c274cb76fb229d0e2bc606ba41f458ed18ab81
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39322
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>

src/arch/arm/isa.hh

@@ -887,6 +887,12 @@ namespace ArmISA
         const Params &params() const;
 
         ISA(const Params &p);
+
+        uint64_t
+        getExecutingAsid() const override
+        {
+            return readMiscRegNoEffect(MISCREG_CONTEXTIDR);
+        }
     };
 }
 

src/arch/arm/utility.hh

@@ -411,12 +411,6 @@ advancePC(PCState &pc, const StaticInstPtr &inst)
 Addr truncPage(Addr addr);
 Addr roundPage(Addr addr);
 
-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-    return tc->readMiscReg(MISCREG_CONTEXTIDR);
-}
-
 // Decodes the register index to access based on the fields used in a MSR
 // or MRS instruction
 bool

src/arch/generic/isa.hh

@@ -54,6 +54,8 @@ class BaseISA : public SimObject
   public:
     virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) {}
     virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
+
+    virtual uint64_t getExecutingAsid() const { return 0; }
 };
 
 #endif // __ARCH_GENERIC_ISA_HH__

src/arch/mips/utility.hh

@@ -108,12 +108,6 @@ advancePC(PCState &pc, const StaticInstPtr &inst)
     pc.advance();
 }
 
-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-    return 0;
-}
-
 };
 
 

src/arch/power/utility.hh

@@ -66,12 +66,6 @@ inUserMode(ThreadContext *tc)
     return 0;
 }
 
-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-    return 0;
-}
-
 } // namespace PowerISA
 
 

src/arch/riscv/utility.hh

@@ -176,12 +176,6 @@ inUserMode(ThreadContext *tc)
     return true;
 }
 
-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-    return 0;
-}
-
 } // namespace RiscvISA
 
 #endif // __ARCH_RISCV_UTILITY_HH__

src/arch/sparc/isa.hh

@@ -215,6 +215,11 @@ class ISA : public BaseISA
     int flattenCCIndex(int reg) const { return reg; }
     int flattenMiscIndex(int reg) const { return reg; }
 
+    uint64_t
+    getExecutingAsid() const override
+    {
+        return readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
+    }
 
     typedef SparcISAParams Params;
     const Params &params() const;

src/arch/sparc/utility.hh

@@ -70,12 +70,6 @@ advancePC(PCState &pc, const StaticInstPtr &inst)
     inst->advancePC(pc);
 }
 
-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-    return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
-}
-
 } // namespace SparcISA
 
 #endif

src/arch/x86/utility.hh

@@ -77,13 +77,6 @@ namespace X86ISA
         inst->advancePC(pc);
     }
 
-    inline uint64_t
-    getExecutingAsid(ThreadContext *tc)
-    {
-        return 0;
-    }
-
-
     /**
      * Reconstruct the rflags register from the internal gem5 register
      * state.

src/cpu/exetrace.cc

@@ -66,8 +66,10 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
         if (!in_user_mode && !Debug::ExecKernel) return;
     }
 
-    if (Debug::ExecAsid)
-        outs << "A" << std::dec << TheISA::getExecutingAsid(thread) << " ";
+    if (Debug::ExecAsid) {
+        outs << "A" << std::dec <<
+            thread->getIsaPtr()->getExecutingAsid() << " ";
+    }
 
     if (Debug::ExecThread)
         outs << "T" << thread->threadId() << " : ";