From cd8a278ec6c1f5e904aff36f886e25733a5b755c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 17 Jan 2021 23:23:39 -0800 Subject: [PATCH] arch,cpu: Move getExecutingAsid to the ISA class. This function was switched based on the ISA, and returned 0 on everything except SPARC and ARM. It was used only when tracing instruction execution with --debug-flags=Exec. Change-Id: I70c274cb76fb229d0e2bc606ba41f458ed18ab81 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39322 Maintainer: Gabe Black Tested-by: kokoro Reviewed-by: Gabe Black --- src/arch/arm/isa.hh | 6 ++++++ src/arch/arm/utility.hh | 6 ------ src/arch/generic/isa.hh | 2 ++ src/arch/mips/utility.hh | 6 ------ src/arch/power/utility.hh | 6 ------ src/arch/riscv/utility.hh | 6 ------ src/arch/sparc/isa.hh | 5 +++++ src/arch/sparc/utility.hh | 6 ------ src/arch/x86/utility.hh | 7 ------- src/cpu/exetrace.cc | 6 ++++-- 10 files changed, 17 insertions(+), 39 deletions(-) diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 133c8248a7..a97b1a57a2 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -887,6 +887,12 @@ namespace ArmISA const Params ¶ms() const; ISA(const Params &p); + + uint64_t + getExecutingAsid() const override + { + return readMiscRegNoEffect(MISCREG_CONTEXTIDR); + } }; } diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 6ec6403966..453e461d77 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -411,12 +411,6 @@ advancePC(PCState &pc, const StaticInstPtr &inst) Addr truncPage(Addr addr); Addr roundPage(Addr addr); -inline uint64_t -getExecutingAsid(ThreadContext *tc) -{ - return tc->readMiscReg(MISCREG_CONTEXTIDR); -} - // Decodes the register index to access based on the fields used in a MSR // or MRS instruction bool diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh index c1b87341be..7d5daa84ce 100644 --- a/src/arch/generic/isa.hh +++ b/src/arch/generic/isa.hh @@ -54,6 +54,8 @@ class BaseISA : public SimObject public: virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) {} virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; } + + virtual uint64_t getExecutingAsid() const { return 0; } }; #endif // __ARCH_GENERIC_ISA_HH__ diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index c156c82cc8..23d92c1c49 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -108,12 +108,6 @@ advancePC(PCState &pc, const StaticInstPtr &inst) pc.advance(); } -inline uint64_t -getExecutingAsid(ThreadContext *tc) -{ - return 0; -} - }; diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh index ba28f07200..3a4b16c516 100644 --- a/src/arch/power/utility.hh +++ b/src/arch/power/utility.hh @@ -66,12 +66,6 @@ inUserMode(ThreadContext *tc) return 0; } -inline uint64_t -getExecutingAsid(ThreadContext *tc) -{ - return 0; -} - } // namespace PowerISA diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh index d4cf221753..816d36cd45 100644 --- a/src/arch/riscv/utility.hh +++ b/src/arch/riscv/utility.hh @@ -176,12 +176,6 @@ inUserMode(ThreadContext *tc) return true; } -inline uint64_t -getExecutingAsid(ThreadContext *tc) -{ - return 0; -} - } // namespace RiscvISA #endif // __ARCH_RISCV_UTILITY_HH__ diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index 288138413c..21143dd384 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -215,6 +215,11 @@ class ISA : public BaseISA int flattenCCIndex(int reg) const { return reg; } int flattenMiscIndex(int reg) const { return reg; } + uint64_t + getExecutingAsid() const override + { + return readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT); + } typedef SparcISAParams Params; const Params ¶ms() const; diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 4738eb438d..3f36f0388e 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -70,12 +70,6 @@ advancePC(PCState &pc, const StaticInstPtr &inst) inst->advancePC(pc); } -inline uint64_t -getExecutingAsid(ThreadContext *tc) -{ - return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT); -} - } // namespace SparcISA #endif diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 39a142c2ab..50f65eff99 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -77,13 +77,6 @@ namespace X86ISA inst->advancePC(pc); } - inline uint64_t - getExecutingAsid(ThreadContext *tc) - { - return 0; - } - - /** * Reconstruct the rflags register from the internal gem5 register * state. diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 7bf60e7489..e144743397 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -66,8 +66,10 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) if (!in_user_mode && !Debug::ExecKernel) return; } - if (Debug::ExecAsid) - outs << "A" << std::dec << TheISA::getExecutingAsid(thread) << " "; + if (Debug::ExecAsid) { + outs << "A" << std::dec << + thread->getIsaPtr()->getExecutingAsid() << " "; + } if (Debug::ExecThread) outs << "T" << thread->threadId() << " : ";