derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: MISCREG_AT_S1E2R/W are executable from S state (#1322)

Browse Source 
Change-Id: Ieaebdf0d62b5115f8085f478b2da105633b6a26a

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-07-04 09:37:17 +01:00
committed by GitHub
parent baf2a9b917
commit c9d9108978
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/arm/regs/misc.cc
View File

@@ -5446,9 +5446,9 @@ ISA::initializeMiscRegMetadata()
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tpc, &HFGITR::dccivac>)
.writes(1);
InitReg(MISCREG_AT_S1E2R_Xt)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_AT_S1E2W_Xt)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_AT_S12E1R_Xt)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_AT_S12E1W_Xt)