From c9d91089781233d91c0d8ecc8e2b2ec89b91ed1e Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 4 Jul 2024 09:37:17 +0100 Subject: [PATCH] arch-arm: MISCREG_AT_S1E2R/W are executable from S state (#1322) Change-Id: Ieaebdf0d62b5115f8085f478b2da105633b6a26a Signed-off-by: Giacomo Travaglini --- src/arch/arm/regs/misc.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index b7779fff76..463d0720f9 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -5446,9 +5446,9 @@ ISA::initializeMiscRegMetadata() .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tpc, &HFGITR::dccivac>) .writes(1); InitReg(MISCREG_AT_S1E2R_Xt) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_AT_S1E2W_Xt) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_AT_S12E1R_Xt) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_AT_S12E1W_Xt)