arch-arm: Implement the L2 TLB as a 5-way set associative

Change-Id: I65d7a384f6d54989cec3c431090c35285011849f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/ArmMMU.py

@@ -72,7 +72,9 @@ class ArmMMU(BaseMMU):
     cxx_header = "arch/arm/mmu.hh"
 
     # L2 TLBs
-    l2_shared = ArmTLB(entry_type="unified", size=1280, partial_levels=["L2"])
+    l2_shared = ArmTLB(
+        entry_type="unified", size=1280, assoc=5, partial_levels=["L2"]
+    )
 
     # L1 TLBs
     itb = ArmTLB(entry_type="instruction", next_level=Parent.l2_shared)