diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index 8cafc2c624..8a7cb80a75 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -72,7 +72,9 @@ class ArmMMU(BaseMMU):
     cxx_header = "arch/arm/mmu.hh"
 
     # L2 TLBs
-    l2_shared = ArmTLB(entry_type="unified", size=1280, partial_levels=["L2"])
+    l2_shared = ArmTLB(
+        entry_type="unified", size=1280, assoc=5, partial_levels=["L2"]
+    )
 
     # L1 TLBs
     itb = ArmTLB(entry_type="instruction", next_level=Parent.l2_shared)