From c974bca123976a3d641be11b6067edb96be2bc9a Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 15 Jul 2024 23:57:35 +0100
Subject: [PATCH] arch-arm: Implement the L2 TLB as a 5-way set associative

Change-Id: I65d7a384f6d54989cec3c431090c35285011849f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
---
 src/arch/arm/ArmMMU.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index 8cafc2c624..8a7cb80a75 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -72,7 +72,9 @@ class ArmMMU(BaseMMU):
     cxx_header = "arch/arm/mmu.hh"
 
     # L2 TLBs
-    l2_shared = ArmTLB(entry_type="unified", size=1280, partial_levels=["L2"])
+    l2_shared = ArmTLB(
+        entry_type="unified", size=1280, assoc=5, partial_levels=["L2"]
+    )
 
     # L1 TLBs
     itb = ArmTLB(entry_type="instruction", next_level=Parent.l2_shared)