cpu: This commit updates cpu FUs according to new Simd types

This commit updates cpu by removing VectorXXX types and updates
    FUs according to the newer SimdXXX ones. This is part of the
    homogenization of RISCV Vector instruction types, which moved
    from VectorXXX to SimdXXX.

Change-Id: I84baccd099b73a11cf26dd714487a9f272671d3d

src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py

@@ -76,10 +76,6 @@ class U74MiscFU(MinorDefaultMiscFU):
     pass
 
 
-class U74VecFU(MinorDefaultVecFU):
-    pass
-
-
 class U74FUPool(MinorFUPool):
     funcUnits = [
         U74IntFU(),
@@ -91,7 +87,6 @@ class U74FUPool(MinorFUPool):
         U74MemReadFU(),
         U74MemWriteFU(),
         U74MiscFU(),
-        U74VecFU(),
     ]