arch-riscv: This commit adds new instruction types to RISC-V

This commit adds some more detailed instruction types for RISC-V
    Vector. Concretely, it substitutes VectorIntegerArith,
    VectorFloatArith, VectorIntegerReduce and VectorFloatReduce with
    more specific types related to the operation that each instruction
    performs, being consistent with SimdXXX ones.

Change-Id: Iaffa74871ccc56d8c3627e1f1e111b9bc9e864af

src/arch/riscv/insts/vector.cc

@@ -414,7 +414,7 @@ VMvWholeMicroInst::generateDisassembly(Addr pc,
 VMaskMergeMicroInst::VMaskMergeMicroInst(ExtMachInst extMachInst,
     uint8_t _dstReg, uint8_t _numSrcs, uint32_t _vlen, size_t _elemSize)
     : VectorArithMicroInst("vmask_mv_micro", extMachInst,
-                            VectorIntegerArithOp, 0, 0),
+                            SimdAddOp, 0, 0),
       vlen(_vlen),
       elemSize(_elemSize)
 {
@@ -503,7 +503,7 @@ VxsatMicroInst::generateDisassembly(Addr pc,
 
 VlFFTrimVlMicroOp::VlFFTrimVlMicroOp(ExtMachInst _machInst, uint32_t _microVl,
     uint32_t _microIdx, uint32_t _vlen, std::vector<StaticInstPtr>& _microops)
-    : VectorMicroInst("vlff_trimvl_v_micro", _machInst, VectorConfigOp,
+    : VectorMicroInst("vlff_trimvl_v_micro", _machInst, SimdConfigOp,
                       _microVl, _microIdx, _vlen),
       microops(_microops)
 {
@@ -618,7 +618,7 @@ VlSegDeIntrlvMicroInst::VlSegDeIntrlvMicroInst(ExtMachInst extMachInst, uint32_t
                         uint32_t _microIdx, uint32_t _numMicroops,
                         uint32_t _field, uint32_t _vlen, uint32_t _sizeOfElement)
     : VectorArithMicroInst("vlseg_deintrlv_micro", extMachInst,
-                            VectorIntegerArithOp, 0, 0),
+                            SimdAddOp, 0, 0),
         vlen(_vlen)
 {
     setRegIdxArrays(
@@ -715,7 +715,7 @@ VsSegIntrlvMicroInst::VsSegIntrlvMicroInst(ExtMachInst extMachInst, uint32_t _mi
                         uint32_t _microIdx, uint32_t _numMicroops,
                         uint32_t _field, uint32_t _vlen, uint32_t _sizeOfElement)
     : VectorArithMicroInst("vsseg_reintrlv_micro", extMachInst,
-                            VectorIntegerArithOp, 0, 0),
+                            SimdAddOp, 0, 0),
         vlen(_vlen)
 {
     setRegIdxArrays(

src/arch/riscv/insts/vector.hh

@@ -569,7 +569,7 @@ class VxsatMicroInst : public VectorArithMicroInst
   public:
     VxsatMicroInst(bool* Vxsat, ExtMachInst extMachInst)
         : VectorArithMicroInst("vxsat_micro", extMachInst,
-          VectorIntegerArithOp, 0, 0)
+          SimdMiscOp, 0, 0)
     {
         vxsat = Vxsat;
     }

src/arch/riscv/isa/templates/vector_mem.isa

@@ -82,7 +82,7 @@ def template VleConstructor {{
         micro_vl = std::min(remaining_vl -= micro_vlmax, micro_vlmax);
     }
 
-    if (_opClass == VectorUnitStrideFaultOnlyFirstLoadOp) {
+    if (_opClass == SimdUnitStrideFaultOnlyFirstLoadOp) {
         microop = new VlFFTrimVlMicroOp(_machInst, this->vl, num_microops,
                                         vlen, microops);
         this->microops.push_back(microop);