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arch-arm: This commit fixes two RISC-V inst types used in SVE

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This commit fixes two RISC-V instruction types (VectorXXX) that
    were used in ARM SVE to the proper SimdXXX ones.

Change-Id: Id632926a89ae2395234f3cf34adeab63844bdd57
This commit is contained in:
Ivan Fernandez
2024-02-28 10:10:29 +01:00
committed by Ivan Fernandez
parent dd5a30d41e
commit 274795c6ee
1 changed files with 4 additions and 4 deletions
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8
src/arch/arm/isa/insts/sve.isa
View File

@@ -4426,19 +4426,19 @@ let {{
# ADCLT
adcltCode = 'res = srcElem1 + srcElem2 + carryIn;'
sveTerInstUnpred('adclt', 'Adclt', 'VectorIntegerArithOp', unsignedTypes,
sveTerInstUnpred('adclt', 'Adclt', 'SimdAddOp', unsignedTypes,
adcltCode, isTop=True, isAdd=True)
# ADCLB
adclbCode = 'res = srcElem1 + srcElem2 + carryIn;'
sveTerInstUnpred('adclb', 'Adclb', 'VectorIntegerArithOp', unsignedTypes,
sveTerInstUnpred('adclb', 'Adclb', 'SimdAddOp', unsignedTypes,
adclbCode, isTop=False, isAdd=True)
# SBCLT
sbcltCode = 'res = srcElem1 + ~(srcElem2) + carryIn;'
sveTerInstUnpred('sbclt', 'Sbclt', 'VectorIntegerArithOp', unsignedTypes,
sveTerInstUnpred('sbclt', 'Sbclt', 'SimdAddOp', unsignedTypes,
sbcltCode, isTop=True, isAdd=False)
# SBCLB
sbclbCode = 'res = srcElem1 + ~(srcElem2) + carryIn;'
sveTerInstUnpred('sbclb', 'Sbclb', 'VectorIntegerArithOp', unsignedTypes,
sveTerInstUnpred('sbclb', 'Sbclb', 'SimdAddOp', unsignedTypes,
sbclbCode, isTop=False, isAdd=False)
mmlaCode = ('destElem += srcElemA * srcElemB')
# SMMLA (vectors)