From 274795c6eeb02006ae394c65d27c157e3829095c Mon Sep 17 00:00:00 2001 From: Ivan Fernandez Date: Wed, 28 Feb 2024 10:10:29 +0100 Subject: [PATCH] arch-arm: This commit fixes two RISC-V inst types used in SVE This commit fixes two RISC-V instruction types (VectorXXX) that were used in ARM SVE to the proper SimdXXX ones. Change-Id: Id632926a89ae2395234f3cf34adeab63844bdd57 --- src/arch/arm/isa/insts/sve.isa | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa index 1db3a8969a..148a31fdbc 100644 --- a/src/arch/arm/isa/insts/sve.isa +++ b/src/arch/arm/isa/insts/sve.isa @@ -4426,19 +4426,19 @@ let {{ # ADCLT adcltCode = 'res = srcElem1 + srcElem2 + carryIn;' - sveTerInstUnpred('adclt', 'Adclt', 'VectorIntegerArithOp', unsignedTypes, + sveTerInstUnpred('adclt', 'Adclt', 'SimdAddOp', unsignedTypes, adcltCode, isTop=True, isAdd=True) # ADCLB adclbCode = 'res = srcElem1 + srcElem2 + carryIn;' - sveTerInstUnpred('adclb', 'Adclb', 'VectorIntegerArithOp', unsignedTypes, + sveTerInstUnpred('adclb', 'Adclb', 'SimdAddOp', unsignedTypes, adclbCode, isTop=False, isAdd=True) # SBCLT sbcltCode = 'res = srcElem1 + ~(srcElem2) + carryIn;' - sveTerInstUnpred('sbclt', 'Sbclt', 'VectorIntegerArithOp', unsignedTypes, + sveTerInstUnpred('sbclt', 'Sbclt', 'SimdAddOp', unsignedTypes, sbcltCode, isTop=True, isAdd=False) # SBCLB sbclbCode = 'res = srcElem1 + ~(srcElem2) + carryIn;' - sveTerInstUnpred('sbclb', 'Sbclb', 'VectorIntegerArithOp', unsignedTypes, + sveTerInstUnpred('sbclb', 'Sbclb', 'SimdAddOp', unsignedTypes, sbclbCode, isTop=False, isAdd=False) mmlaCode = ('destElem += srcElemA * srcElemB') # SMMLA (vectors)