diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index e6a5040b9c..2244dd2ae4 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -100,27 +100,22 @@ class OpClass(Enum):
         "FloatMemWrite",
         "IprAccess",
         "InstPrefetch",
-        "VectorUnitStrideLoad",
-        "VectorUnitStrideStore",
-        "VectorUnitStrideSegmentedStore",
-        "VectorUnitStrideMaskLoad",
-        "VectorUnitStrideMaskStore",
-        "VectorStridedLoad",
-        "VectorStridedStore",
-        "VectorIndexedLoad",
-        "VectorIndexedStore",
-        "VectorUnitStrideFaultOnlyFirstLoad",
-        "VectorWholeRegisterLoad",
-        "VectorWholeRegisterStore",
-        "VectorIntegerArith",
-        "VectorUnitStrideSegmentedLoad",
-        "VectorFloatArith",
-        "VectorFloatConvert",
-        "VectorIntegerReduce",
-        "VectorFloatReduce",
-        "VectorMisc",
-        "VectorIntegerExtension",
-        "VectorConfig",
+        "SimdUnitStrideLoad",
+        "SimdUnitStrideStore",
+        "SimdUnitStrideMaskLoad",
+        "SimdUnitStrideMaskStore",
+        "SimdStridedLoad",
+        "SimdStridedStore",
+        "SimdIndexedLoad",
+        "SimdIndexedStore",
+        "SimdWholeRegisterLoad",
+        "SimdWholeRegisterStore",
+        "SimdUnitStrideFaultOnlyFirstLoad",
+        "SimdUnitStrideSegmentedLoad",
+        "SimdUnitStrideSegmentedStore",
+        "SimdExt",
+        "SimdFloatExt",
+        "SimdConfig",
     ]
 
 
diff --git a/src/cpu/minor/BaseMinorCPU.py b/src/cpu/minor/BaseMinorCPU.py
index 6369981c57..545dfeaee5 100644
--- a/src/cpu/minor/BaseMinorCPU.py
+++ b/src/cpu/minor/BaseMinorCPU.py
@@ -219,6 +219,10 @@ class MinorDefaultFloatSimdFU(MinorFU):
             "Matrix",
             "MatrixMov",
             "MatrixOP",
+            "SimdExt",
+            "SimdFloatExt",
+            "SimdFloatCvt",
+            "SimdConfig",
         ]
     )
 
@@ -234,7 +238,23 @@ class MinorDefaultPredFU(MinorFU):
 
 class MinorDefaultMemFU(MinorFU):
     opClasses = minorMakeOpClassSet(
-        ["MemRead", "MemWrite", "FloatMemRead", "FloatMemWrite"]
+        [
+            "MemRead",
+            "MemWrite",
+            "FloatMemRead",
+            "FloatMemWrite",
+            "SimdUnitStrideLoad",
+            "SimdUnitStrideStore",
+            "SimdUnitStrideMaskLoad",
+            "SimdUnitStrideMaskStore",
+            "SimdStridedLoad",
+            "SimdStridedStore",
+            "SimdIndexedLoad",
+            "SimdIndexedStore",
+            "SimdUnitStrideFaultOnlyFirstLoad",
+            "SimdWholeRegisterLoad",
+            "SimdWholeRegisterStore",
+        ]
     )
     timings = [
         MinorFUTiming(
@@ -249,34 +269,6 @@ class MinorDefaultMiscFU(MinorFU):
     opLat = 1
 
 
-class MinorDefaultVecFU(MinorFU):
-    opClasses = minorMakeOpClassSet(
-        [
-            "VectorUnitStrideLoad",
-            "VectorUnitStrideStore",
-            "VectorUnitStrideMaskLoad",
-            "VectorUnitStrideMaskStore",
-            "VectorStridedLoad",
-            "VectorStridedStore",
-            "VectorIndexedLoad",
-            "VectorIndexedStore",
-            "VectorUnitStrideFaultOnlyFirstLoad",
-            "VectorUnitStrideSegmentedLoad",
-            "VectorWholeRegisterLoad",
-            "VectorWholeRegisterStore",
-            "VectorIntegerArith",
-            "VectorFloatArith",
-            "VectorFloatConvert",
-            "VectorIntegerReduce",
-            "VectorFloatReduce",
-            "VectorMisc",
-            "VectorIntegerExtension",
-            "VectorConfig",
-        ]
-    )
-    opLat = 1
-
-
 class MinorDefaultFUPool(MinorFUPool):
     funcUnits = [
         MinorDefaultIntFU(),
@@ -287,7 +279,6 @@ class MinorDefaultFUPool(MinorFUPool):
         MinorDefaultPredFU(),
         MinorDefaultMemFU(),
         MinorDefaultMiscFU(),
-        MinorDefaultVecFU(),
     ]
 
 
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index 617cef9749..ab01b4aa27 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -106,6 +106,9 @@ class SIMD_Unit(FUDesc):
         OpDesc(opClass="SimdReduceCmp"),
         OpDesc(opClass="SimdFloatReduceAdd"),
         OpDesc(opClass="SimdFloatReduceCmp"),
+        OpDesc(opClass="SimdExt"),
+        OpDesc(opClass="SimdFloatExt"),
+        OpDesc(opClass="SimdConfig"),
     ]
     count = 4
 
@@ -116,12 +119,29 @@ class PredALU(FUDesc):
 
 
 class ReadPort(FUDesc):
-    opList = [OpDesc(opClass="MemRead"), OpDesc(opClass="FloatMemRead")]
+    opList = [
+        OpDesc(opClass="MemRead"),
+        OpDesc(opClass="FloatMemRead"),
+        OpDesc(opClass="SimdUnitStrideLoad"),
+        OpDesc(opClass="SimdUnitStrideMaskLoad"),
+        OpDesc(opClass="SimdStridedLoad"),
+        OpDesc(opClass="SimdIndexedLoad"),
+        OpDesc(opClass="SimdUnitStrideFaultOnlyFirstLoad"),
+        OpDesc(opClass="SimdWholeRegisterLoad"),
+    ]
     count = 0
 
 
 class WritePort(FUDesc):
-    opList = [OpDesc(opClass="MemWrite"), OpDesc(opClass="FloatMemWrite")]
+    opList = [
+        OpDesc(opClass="MemWrite"),
+        OpDesc(opClass="FloatMemWrite"),
+        OpDesc(opClass="SimdUnitStrideStore"),
+        OpDesc(opClass="SimdUnitStrideMaskStore"),
+        OpDesc(opClass="SimdStridedStore"),
+        OpDesc(opClass="SimdIndexedStore"),
+        OpDesc(opClass="SimdWholeRegisterStore"),
+    ]
     count = 0
 
 
@@ -131,6 +151,17 @@ class RdWrPort(FUDesc):
         OpDesc(opClass="MemWrite"),
         OpDesc(opClass="FloatMemRead"),
         OpDesc(opClass="FloatMemWrite"),
+        OpDesc(opClass="SimdUnitStrideLoad"),
+        OpDesc(opClass="SimdUnitStrideStore"),
+        OpDesc(opClass="SimdUnitStrideMaskLoad"),
+        OpDesc(opClass="SimdUnitStrideMaskStore"),
+        OpDesc(opClass="SimdStridedLoad"),
+        OpDesc(opClass="SimdStridedStore"),
+        OpDesc(opClass="SimdIndexedLoad"),
+        OpDesc(opClass="SimdIndexedStore"),
+        OpDesc(opClass="SimdUnitStrideFaultOnlyFirstLoad"),
+        OpDesc(opClass="SimdWholeRegisterLoad"),
+        OpDesc(opClass="SimdWholeRegisterStore"),
     ]
     count = 4
 
diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index 54e9c272db..c8812ab36b 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -108,35 +108,30 @@ static const OpClass MemReadOp = enums::MemRead;
 static const OpClass MemWriteOp = enums::MemWrite;
 static const OpClass FloatMemReadOp = enums::FloatMemRead;
 static const OpClass FloatMemWriteOp = enums::FloatMemWrite;
+static const OpClass SimdUnitStrideLoadOp = enums::SimdUnitStrideLoad;
+static const OpClass SimdUnitStrideStoreOp = enums::SimdUnitStrideStore;
+static const OpClass SimdUnitStrideMaskLoadOp
+             = enums::SimdUnitStrideMaskLoad;
+static const OpClass SimdUnitStrideMaskStoreOp
+             = enums::SimdUnitStrideMaskStore;
+static const OpClass SimdStridedLoadOp = enums::SimdStridedLoad;
+static const OpClass SimdStridedStoreOp = enums::SimdStridedStore;
+static const OpClass SimdIndexedLoadOp = enums::SimdIndexedLoad;
+static const OpClass SimdIndexedStoreOp = enums::SimdIndexedStore;
+static const OpClass SimdUnitStrideFaultOnlyFirstLoadOp
+             = enums::SimdUnitStrideFaultOnlyFirstLoad;
+static const OpClass SimdWholeRegisterLoadOp
+             = enums::SimdWholeRegisterLoad;
+static const OpClass SimdWholeRegisterStoreOp
+             = enums::SimdWholeRegisterStore;
 static const OpClass IprAccessOp = enums::IprAccess;
 static const OpClass InstPrefetchOp = enums::InstPrefetch;
-static const OpClass VectorUnitStrideLoadOp = enums::VectorUnitStrideLoad;
-static const OpClass VectorUnitStrideStoreOp = enums::VectorUnitStrideStore;
-static const OpClass VectorUnitStrideMaskLoadOp
-             = enums::VectorUnitStrideMaskLoad;
-static const OpClass VectorUnitStrideMaskStoreOp
-             = enums::VectorUnitStrideMaskStore;
-static const OpClass VectorStridedLoadOp = enums::VectorStridedLoad;
-static const OpClass VectorStridedStoreOp = enums::VectorStridedStore;
-static const OpClass VectorIndexedLoadOp = enums::VectorIndexedLoad;
-static const OpClass VectorIndexedStoreOp = enums::VectorIndexedStore;
-static const OpClass VectorUnitStrideFaultOnlyFirstLoadOp
-             = enums::VectorUnitStrideFaultOnlyFirstLoad;
-static const OpClass VectorWholeRegisterLoadOp
-             = enums::VectorWholeRegisterLoad;
-static const OpClass VectorWholeRegisterStoreOp
-             = enums::VectorWholeRegisterStore;
-static const OpClass VectorIntegerArithOp = enums::VectorIntegerArith;
-static const OpClass VectorFloatArithOp = enums::VectorFloatArith;
-static const OpClass VectorFloatConvertOp = enums::VectorFloatConvert;
-static const OpClass VectorIntegerReduceOp = enums::VectorIntegerReduce;
-static const OpClass VectorFloatReduceOp = enums::VectorFloatReduce;
-static const OpClass VectorMiscOp = enums::VectorMisc;
-static const OpClass VectorIntegerExtensionOp = enums::VectorIntegerExtension;
-static const OpClass VectorUnitStrideSegmentedLoadOp = enums::VectorUnitStrideSegmentedLoad;
-static const OpClass VectorConfigOp = enums::VectorConfig;
-static const OpClass VectorUnitStrideSegmentedStoreOp
-             = enums::VectorUnitStrideSegmentedStore;
+static const OpClass SimdUnitStrideSegmentedLoadOp = enums::SimdUnitStrideSegmentedLoad;
+static const OpClass SimdUnitStrideSegmentedStoreOp
+             = enums::SimdUnitStrideSegmentedStore;
+static const OpClass SimdExtOp = enums::SimdExt;
+static const OpClass SimdFloatExtOp = enums::SimdFloatExt;
+static const OpClass SimdConfigOp = enums::SimdConfig;
 static const OpClass Num_OpClasses = enums::Num_OpClass;
 
 } // namespace gem5
diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
index 179e466e7a..451afe46ba 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
@@ -76,10 +76,6 @@ class U74MiscFU(MinorDefaultMiscFU):
     pass
 
 
-class U74VecFU(MinorDefaultVecFU):
-    pass
-
-
 class U74FUPool(MinorFUPool):
     funcUnits = [
         U74IntFU(),
@@ -91,7 +87,6 @@ class U74FUPool(MinorFUPool):
         U74MemReadFU(),
         U74MemWriteFU(),
         U74MiscFU(),
-        U74VecFU(),
     ]