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arch-arm,cpu: Add a class for ops for vec reg elements.

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This lets a caller print the name of a register in a friendly way
without having to know how many elements go with each vector register.

Change-Id: I85598c078c604f1bebdba797308102482639c209
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49163
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-09 23:35:58 -07:00
parent c3880c2c46
commit c537d9ad10
3 changed files with 25 additions and 1 deletions
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5
src/arch/arm/isa.cc
View File

@@ -80,6 +80,8 @@ class MiscRegClassOps : public RegClassOps
}
} miscRegClassOps;
VecElemRegClassOps vecRegElemClassOps(NumVecElemPerVecReg);
ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
@@ -87,7 +89,8 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO);
_regClasses.emplace_back(0);
_regClasses.emplace_back(NumVecRegs);
_regClasses.emplace_back(NumVecRegs * TheISA::NumVecElemPerVecReg);
_regClasses.emplace_back(NumVecRegs * NumVecElemPerVecReg,
vecRegElemClassOps);
_regClasses.emplace_back(NumVecPredRegs);
_regClasses.emplace_back(NUM_CCREGS);
_regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps);

8
src/cpu/reg_class.cc
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@@ -50,6 +50,14 @@ DefaultRegClassOps::regName(const RegId &id) const
return csprintf("r%d", id.index());
}
std::string
VecElemRegClassOps::regName(const RegId &id) const
{
RegIndex reg_idx = id.index() / elemsPerVec;
RegIndex elem_idx = id.index() % elemsPerVec;
return csprintf("v%d[%d]", reg_idx, elem_idx);
}
const char *RegId::regClassStrings[] = {
"IntRegClass",
"FloatRegClass",

13
src/cpu/reg_class.hh
View File

@@ -79,6 +79,19 @@ class DefaultRegClassOps : public RegClassOps
std::string regName(const RegId &id) const override;
};
class VecElemRegClassOps : public RegClassOps
{
protected:
size_t elemsPerVec;
public:
explicit VecElemRegClassOps(size_t elems_per_vec) :
elemsPerVec(elems_per_vec)
{}
std::string regName(const RegId &id) const override;
};
class RegClass
{
private: