diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index ed3bea2885..5c8c7436de 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -80,6 +80,8 @@ class MiscRegClassOps : public RegClassOps } } miscRegClassOps; +VecElemRegClassOps vecRegElemClassOps(NumVecElemPerVecReg); + ISA::ISA(const Params &p) : BaseISA(p), system(NULL), _decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop), afterStartup(false) @@ -87,7 +89,8 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL), _regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO); _regClasses.emplace_back(0); _regClasses.emplace_back(NumVecRegs); - _regClasses.emplace_back(NumVecRegs * TheISA::NumVecElemPerVecReg); + _regClasses.emplace_back(NumVecRegs * NumVecElemPerVecReg, + vecRegElemClassOps); _regClasses.emplace_back(NumVecPredRegs); _regClasses.emplace_back(NUM_CCREGS); _regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps); diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc index fc39e42a5e..b6678383bf 100644 --- a/src/cpu/reg_class.cc +++ b/src/cpu/reg_class.cc @@ -50,6 +50,14 @@ DefaultRegClassOps::regName(const RegId &id) const return csprintf("r%d", id.index()); } +std::string +VecElemRegClassOps::regName(const RegId &id) const +{ + RegIndex reg_idx = id.index() / elemsPerVec; + RegIndex elem_idx = id.index() % elemsPerVec; + return csprintf("v%d[%d]", reg_idx, elem_idx); +} + const char *RegId::regClassStrings[] = { "IntRegClass", "FloatRegClass", diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh index 3c3a6569e0..da6be67ea8 100644 --- a/src/cpu/reg_class.hh +++ b/src/cpu/reg_class.hh @@ -79,6 +79,19 @@ class DefaultRegClassOps : public RegClassOps std::string regName(const RegId &id) const override; }; +class VecElemRegClassOps : public RegClassOps +{ + protected: + size_t elemsPerVec; + + public: + explicit VecElemRegClassOps(size_t elems_per_vec) : + elemsPerVec(elems_per_vec) + {} + + std::string regName(const RegId &id) const override; +}; + class RegClass { private: