util: Make x86-add-xcr0 work for testlib checkpoints

Change-Id: I7b93d7afc7710bd43412a77a204ce8838d0bfb4e
This commit is contained in:
Matthew Poremba
2024-04-29 11:45:55 -07:00
parent a6138777e2
commit c495ff84ec

View File

@@ -41,6 +41,14 @@ def upgrader(cpt):
if cpt.get(sec, "isaName") == "x86":
regVals = cpt.get(sec, "regVal")
# Add the default value of XCR0 (1) if missing
regVals = f"{regVals} 1"
cpt.set(sec, "regVal", regVals)
elif re.search(rf"board\.processor\.cores.*isa$", sec):
# ISA name doesn't appear to be anywhere in the checkpoint.
# Assume it is X86.
regVals = cpt.get(sec, "regVal")
# Add the default value of XCR0 (1) if missing
regVals = f"{regVals} 1"
cpt.set(sec, "regVal", regVals)