From c495ff84ec40554ff66a422afaa3baa9bd1306db Mon Sep 17 00:00:00 2001
From: Matthew Poremba <matthew.poremba@amd.com>
Date: Mon, 29 Apr 2024 11:45:55 -0700
Subject: [PATCH] util: Make x86-add-xcr0 work for testlib checkpoints

Change-Id: I7b93d7afc7710bd43412a77a204ce8838d0bfb4e
---
 util/cpt_upgraders/x86-add-xcr0.py | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/util/cpt_upgraders/x86-add-xcr0.py b/util/cpt_upgraders/x86-add-xcr0.py
index fe81fcde99..0e860013c6 100644
--- a/util/cpt_upgraders/x86-add-xcr0.py
+++ b/util/cpt_upgraders/x86-add-xcr0.py
@@ -44,3 +44,11 @@ def upgrader(cpt):
                 # Add the default value of XCR0 (1) if missing
                 regVals = f"{regVals} 1"
                 cpt.set(sec, "regVal", regVals)
+        elif re.search(rf"board\.processor\.cores.*isa$", sec):
+            # ISA name doesn't appear to be anywhere in the checkpoint.
+            # Assume it is X86.
+            regVals = cpt.get(sec, "regVal")
+
+            # Add the default value of XCR0 (1) if missing
+            regVals = f"{regVals} 1"
+            cpt.set(sec, "regVal", regVals)