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arch-arm: Move generateTrap from MiscRegOp to ArmStaticInst (#1560)

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System(Misc) register accesses are not the only trappable instructions.
We move the exception generation logic (generateTrap) from the
MiscRegOp64 to the base ArmStaticInst
This commit is contained in:
Giacomo Travaglini
2024-09-23 19:37:29 +02:00
committed by GitHub
parent e85592da14 5eec041e2d
commit c3d356b43d
4 changed files with 32 additions and 87 deletions
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16
src/arch/arm/insts/misc64.cc
View File

@@ -128,22 +128,6 @@ MiscRegOp64::generateTrap(ExceptionLevel el) const
return generateTrap(el, ExceptionClass::TRAPPED_MSR_MRS_64, iss());
}
Fault
MiscRegOp64::generateTrap(ExceptionLevel el, ExceptionClass ec,
uint32_t iss) const
{
switch (el) {
case EL1:
return std::make_shared<SupervisorTrap>(getEMI(), iss, ec);
case EL2:
return std::make_shared<HypervisorTrap>(getEMI(), iss, ec);
case EL3:
return std::make_shared<SecureMonitorTrap>(getEMI(), iss, ec);
default:
panic("Invalid EL: %d\n", el);
}
}
RegVal
MiscRegImmOp64::miscRegImm() const
{

3
src/arch/arm/insts/misc64.hh
View File

@@ -174,9 +174,8 @@ class MiscRegOp64 : public ArmISA::ArmStaticInst
bool miscRead() const { return _miscRead; }
using ArmISA::ArmStaticInst::generateTrap;
Fault generateTrap(ArmISA::ExceptionLevel el) const;
Fault generateTrap(ArmISA::ExceptionLevel el,
ArmISA::ExceptionClass ec, uint32_t iss) const;
};
class MiscRegImmOp64 : public MiscRegOp64

96
src/arch/arm/insts/static_inst.cc
View File

@@ -654,23 +654,9 @@ ArmStaticInst::softwareBreakpoint32(ExecContext *xc, uint16_t imm) const
Fault
ArmStaticInst::advSIMDFPAccessTrap64(ExceptionLevel el) const
{
switch (el) {
case EL1:
return std::make_shared<SupervisorTrap>(
machInst, 0x1E00000, ExceptionClass::TRAPPED_SIMD_FP);
case EL2:
return std::make_shared<HypervisorTrap>(
machInst, 0x1E00000, ExceptionClass::TRAPPED_SIMD_FP);
case EL3:
return std::make_shared<SecureMonitorTrap>(
machInst, 0x1E00000, ExceptionClass::TRAPPED_SIMD_FP);
default:
panic("Illegal EL in advSIMDFPAccessTrap64\n");
}
return generateTrap(el, ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
}
Fault
ArmStaticInst::checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
{
@@ -871,37 +857,20 @@ ArmStaticInst::checkForWFxTrap32(ThreadContext *tc,
Fault
ArmStaticInst::checkForWFxTrap64(ThreadContext *tc,
ExceptionLevel targetEL,
bool isWfe) const
ExceptionLevel target_el,
bool is_wfe) const
{
// Check if target exception level is implemented.
assert(ArmSystem::haveEL(tc, targetEL));
assert(ArmSystem::haveEL(tc, target_el));
// Check if processor needs to trap at selected exception level
bool trap = isWFxTrapping(tc, targetEL, isWfe);
if (trap) {
uint32_t iss = isWfe? 0x1E00001 : /* WFE Instruction syndrome */
0x1E00000; /* WFI Instruction syndrome */
switch (targetEL) {
case EL1:
return std::make_shared<SupervisorTrap>(
machInst, iss,
ExceptionClass::TRAPPED_WFI_WFE);
case EL2:
return std::make_shared<HypervisorTrap>(
machInst, iss,
ExceptionClass::TRAPPED_WFI_WFE);
case EL3:
return std::make_shared<SecureMonitorTrap>(
machInst, iss,
ExceptionClass::TRAPPED_WFI_WFE);
default:
panic("Unrecognized Exception Level: %d\n", targetEL);
}
if (isWFxTrapping(tc, target_el, is_wfe)) {
uint32_t iss = is_wfe? 0x1E00001 : /* WFE Instruction syndrome */
0x1E00000; /* WFI Instruction syndrome */
return generateTrap(target_el, ExceptionClass::TRAPPED_WFI_WFE, iss);
} else {
return NoFault;
}
return NoFault;
}
Fault
@@ -1007,20 +976,7 @@ ArmStaticInst::undefinedFault64(ThreadContext *tc,
Fault
ArmStaticInst::sveAccessTrap(ExceptionLevel el) const
{
switch (el) {
case EL1:
return std::make_shared<SupervisorTrap>(
machInst, 0, ExceptionClass::TRAPPED_SVE);
case EL2:
return std::make_shared<HypervisorTrap>(
machInst, 0, ExceptionClass::TRAPPED_SVE);
case EL3:
return std::make_shared<SecureMonitorTrap>(
machInst, 0, ExceptionClass::TRAPPED_SVE);
default:
panic("Illegal EL in sveAccessTrap\n");
}
return generateTrap(el, ExceptionClass::TRAPPED_SVE, 0);
}
Fault
@@ -1083,20 +1039,7 @@ ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
Fault
ArmStaticInst::smeAccessTrap(ExceptionLevel el, uint32_t iss) const
{
switch (el) {
case EL1:
return std::make_shared<SupervisorTrap>(
machInst, iss, ExceptionClass::TRAPPED_SME);
case EL2:
return std::make_shared<HypervisorTrap>(
machInst, iss, ExceptionClass::TRAPPED_SME);
case EL3:
return std::make_shared<SecureMonitorTrap>(
machInst, iss, ExceptionClass::TRAPPED_SME);
default:
panic("Illegal EL in smeAccessTrap\n");
}
return generateTrap(el, ExceptionClass::TRAPPED_SME, iss);
}
Fault
@@ -1367,6 +1310,21 @@ ArmStaticInst::getCurSmeVecLenInBits(ThreadContext *tc)
return isa->getCurSmeVecLenInBits();
}
Fault
ArmStaticInst::generateTrap(ExceptionLevel el, ExceptionClass ec,
uint32_t iss) const
{
switch (el) {
case EL1:
return std::make_shared<SupervisorTrap>(getEMI(), iss, ec);
case EL2:
return std::make_shared<HypervisorTrap>(getEMI(), iss, ec);
case EL3:
return std::make_shared<SecureMonitorTrap>(getEMI(), iss, ec);
default:
panic("Invalid EL: %d\n", el);
}
}
} // namespace ArmISA
} // namespace gem5

4
src/arch/arm/insts/static_inst.hh
View File

@@ -633,6 +633,10 @@ class ArmStaticInst : public StaticInst
return std::make_shared<UndefinedInstruction>(
machInst, false, mnemonic, disabled);
}
Fault
generateTrap(ArmISA::ExceptionLevel el,
ArmISA::ExceptionClass ec, uint32_t iss) const;
};
} // namespace ArmISA