From a4c96002007eebd99a72e1afa6fdf621bd4bbf98 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 27 Sep 2023 18:58:06 +0100 Subject: [PATCH 1/2] arch-arm: Move generateTrap from MiscRegOp to ArmStaticInst System(Misc) register accesses are not the only trappable instructions. We move the exception generation logic (generateTrap) from the MiscRegOp64 to the base ArmStaticInst Change-Id: Ie2ba0c39790f50e3e8d504d153025d402283ec95 Signed-off-by: Giacomo Travaglini --- src/arch/arm/insts/misc64.cc | 16 ---------------- src/arch/arm/insts/misc64.hh | 3 +-- src/arch/arm/insts/static_inst.cc | 15 +++++++++++++++ src/arch/arm/insts/static_inst.hh | 4 ++++ 4 files changed, 20 insertions(+), 18 deletions(-) diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 4ad44bfc63..bb1de2cc94 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -128,22 +128,6 @@ MiscRegOp64::generateTrap(ExceptionLevel el) const return generateTrap(el, ExceptionClass::TRAPPED_MSR_MRS_64, iss()); } -Fault -MiscRegOp64::generateTrap(ExceptionLevel el, ExceptionClass ec, - uint32_t iss) const -{ - switch (el) { - case EL1: - return std::make_shared(getEMI(), iss, ec); - case EL2: - return std::make_shared(getEMI(), iss, ec); - case EL3: - return std::make_shared(getEMI(), iss, ec); - default: - panic("Invalid EL: %d\n", el); - } -} - RegVal MiscRegImmOp64::miscRegImm() const { diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh index 78c29e585e..6b94099262 100644 --- a/src/arch/arm/insts/misc64.hh +++ b/src/arch/arm/insts/misc64.hh @@ -174,9 +174,8 @@ class MiscRegOp64 : public ArmISA::ArmStaticInst bool miscRead() const { return _miscRead; } + using ArmISA::ArmStaticInst::generateTrap; Fault generateTrap(ArmISA::ExceptionLevel el) const; - Fault generateTrap(ArmISA::ExceptionLevel el, - ArmISA::ExceptionClass ec, uint32_t iss) const; }; class MiscRegImmOp64 : public MiscRegOp64 diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index a645b39270..86e8cdfa5c 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -1367,6 +1367,21 @@ ArmStaticInst::getCurSmeVecLenInBits(ThreadContext *tc) return isa->getCurSmeVecLenInBits(); } +Fault +ArmStaticInst::generateTrap(ExceptionLevel el, ExceptionClass ec, + uint32_t iss) const +{ + switch (el) { + case EL1: + return std::make_shared(getEMI(), iss, ec); + case EL2: + return std::make_shared(getEMI(), iss, ec); + case EL3: + return std::make_shared(getEMI(), iss, ec); + default: + panic("Invalid EL: %d\n", el); + } +} } // namespace ArmISA } // namespace gem5 diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index cc96dd9269..484017fe88 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -633,6 +633,10 @@ class ArmStaticInst : public StaticInst return std::make_shared( machInst, false, mnemonic, disabled); } + + Fault + generateTrap(ArmISA::ExceptionLevel el, + ArmISA::ExceptionClass ec, uint32_t iss) const; }; } // namespace ArmISA From 5eec041e2dc3bc83a311616a82063cbe1457036f Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 27 Sep 2023 19:10:35 +0100 Subject: [PATCH 2/2] arch-arm: Use generateTrap for SME/SVE/SIMD/WFE/WFI trapping This avoids repeating the same switch construct Change-Id: Ie16c52519b1e1f984284f2f1344a3903a0010d36 Signed-off-by: Giacomo Travaglini --- src/arch/arm/insts/static_inst.cc | 81 +++++-------------------------- 1 file changed, 12 insertions(+), 69 deletions(-) diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 86e8cdfa5c..34155f0f0d 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -654,23 +654,9 @@ ArmStaticInst::softwareBreakpoint32(ExecContext *xc, uint16_t imm) const Fault ArmStaticInst::advSIMDFPAccessTrap64(ExceptionLevel el) const { - switch (el) { - case EL1: - return std::make_shared( - machInst, 0x1E00000, ExceptionClass::TRAPPED_SIMD_FP); - case EL2: - return std::make_shared( - machInst, 0x1E00000, ExceptionClass::TRAPPED_SIMD_FP); - case EL3: - return std::make_shared( - machInst, 0x1E00000, ExceptionClass::TRAPPED_SIMD_FP); - - default: - panic("Illegal EL in advSIMDFPAccessTrap64\n"); - } + return generateTrap(el, ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000); } - Fault ArmStaticInst::checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const { @@ -871,37 +857,20 @@ ArmStaticInst::checkForWFxTrap32(ThreadContext *tc, Fault ArmStaticInst::checkForWFxTrap64(ThreadContext *tc, - ExceptionLevel targetEL, - bool isWfe) const + ExceptionLevel target_el, + bool is_wfe) const { // Check if target exception level is implemented. - assert(ArmSystem::haveEL(tc, targetEL)); + assert(ArmSystem::haveEL(tc, target_el)); // Check if processor needs to trap at selected exception level - bool trap = isWFxTrapping(tc, targetEL, isWfe); - - if (trap) { - uint32_t iss = isWfe? 0x1E00001 : /* WFE Instruction syndrome */ - 0x1E00000; /* WFI Instruction syndrome */ - switch (targetEL) { - case EL1: - return std::make_shared( - machInst, iss, - ExceptionClass::TRAPPED_WFI_WFE); - case EL2: - return std::make_shared( - machInst, iss, - ExceptionClass::TRAPPED_WFI_WFE); - case EL3: - return std::make_shared( - machInst, iss, - ExceptionClass::TRAPPED_WFI_WFE); - default: - panic("Unrecognized Exception Level: %d\n", targetEL); - } + if (isWFxTrapping(tc, target_el, is_wfe)) { + uint32_t iss = is_wfe? 0x1E00001 : /* WFE Instruction syndrome */ + 0x1E00000; /* WFI Instruction syndrome */ + return generateTrap(target_el, ExceptionClass::TRAPPED_WFI_WFE, iss); + } else { + return NoFault; } - - return NoFault; } Fault @@ -1007,20 +976,7 @@ ArmStaticInst::undefinedFault64(ThreadContext *tc, Fault ArmStaticInst::sveAccessTrap(ExceptionLevel el) const { - switch (el) { - case EL1: - return std::make_shared( - machInst, 0, ExceptionClass::TRAPPED_SVE); - case EL2: - return std::make_shared( - machInst, 0, ExceptionClass::TRAPPED_SVE); - case EL3: - return std::make_shared( - machInst, 0, ExceptionClass::TRAPPED_SVE); - - default: - panic("Illegal EL in sveAccessTrap\n"); - } + return generateTrap(el, ExceptionClass::TRAPPED_SVE, 0); } Fault @@ -1083,20 +1039,7 @@ ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const Fault ArmStaticInst::smeAccessTrap(ExceptionLevel el, uint32_t iss) const { - switch (el) { - case EL1: - return std::make_shared( - machInst, iss, ExceptionClass::TRAPPED_SME); - case EL2: - return std::make_shared( - machInst, iss, ExceptionClass::TRAPPED_SME); - case EL3: - return std::make_shared( - machInst, iss, ExceptionClass::TRAPPED_SME); - - default: - panic("Illegal EL in smeAccessTrap\n"); - } + return generateTrap(el, ExceptionClass::TRAPPED_SME, iss); } Fault