tests: Update asmtest script and add more test binaries (#206)
Upload the config script to make it only for riscv asmtest and replace Resource with obtain_resourse. Also adds more test binaries.
This commit is contained in:
Bobby R. Bruce
@@ -31,7 +31,7 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in
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gem5 while still being functinal.
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"""
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from gem5.resources.resource import Resource
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from gem5.resources.resource import obtain_resource
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from gem5.components.processors.cpu_types import (
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get_cpu_types_str_set,
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get_cpu_type_from_str,
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@@ -40,29 +40,13 @@ from gem5.components.memory import SingleChannelDDR3_1600
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from gem5.components.boards.simple_board import SimpleBoard
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from gem5.components.cachehierarchies.classic.no_cache import NoCache
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.components.processors.base_cpu_core import BaseCPUCore
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from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
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from gem5.components.processors.simple_core import SimpleCore
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from gem5.components.boards.mem_mode import MemMode
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.simulate.simulator import Simulator
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from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
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from m5.util import fatal
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from gem5.isas import ISA
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import argparse
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import importlib
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cpu_types_string_map = {
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CPUTypes.ATOMIC: "AtomicSimpleCPU",
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CPUTypes.O3: "O3CPU",
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CPUTypes.TIMING: "TimingSimpleCPU",
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CPUTypes.KVM: "KvmCPU",
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CPUTypes.MINOR: "MinorCPU",
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}
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parser = argparse.ArgumentParser(
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description="A gem5 script for running simple binaries in SE mode."
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description="A gem5 script for testing RISC-V instructions"
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)
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parser.add_argument(
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@@ -73,17 +57,6 @@ parser.add_argument(
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"cpu", type=str, choices=get_cpu_types_str_set(), help="The CPU type used."
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)
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parser.add_argument(
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"isa", type=str, choices=get_isas_str_set(), help="The ISA used"
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)
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parser.add_argument(
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"-b",
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"--base-cpu-processor",
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action="store_true",
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help="Use the BaseCPUProcessor instead of the SimpleProcessor.",
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)
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parser.add_argument(
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"--riscv-32bits",
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action="store_true",
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@@ -98,15 +71,6 @@ parser.add_argument(
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help="The directory in which resources will be downloaded or exist.",
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)
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parser.add_argument(
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"--arguments",
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type=str,
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action="append",
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default=[],
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required=False,
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help="The input arguments for the binary.",
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)
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parser.add_argument(
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"-n",
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"--num-cores",
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@@ -122,45 +86,16 @@ args = parser.parse_args()
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cache_hierarchy = NoCache()
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memory = SingleChannelDDR3_1600()
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isa_enum = get_isa_from_str(args.isa)
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cpu_enum = get_cpu_type_from_str(args.cpu)
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processor = SimpleProcessor(
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cpu_type=get_cpu_type_from_str(args.cpu),
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isa=ISA.RISCV,
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num_cores=args.num_cores,
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)
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if isa_enum == ISA.RISCV and args.riscv_32bits and not args.base_cpu_processor:
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fatal("To use Riscv 32 CPU, the base_cpu_processor must be specify!")
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if args.base_cpu_processor:
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if isa_enum == ISA.RISCV and args.riscv_32bits:
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m5_objects = importlib.import_module("m5.objects")
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cpu_class = getattr(
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m5_objects, f"Riscv32{cpu_types_string_map[cpu_enum]}"
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)
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cores = [
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BaseCPUCore(core=cpu_class(cpu_id=i), isa=isa_enum)
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for i in range(args.num_cores)
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]
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else:
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cores = [
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BaseCPUCore(
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core=SimpleCore.cpu_simobject_factory(
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cpu_type=cpu_enum,
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isa=isa_enum,
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core_id=i,
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),
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isa=isa_enum,
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)
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for i in range(args.num_cores)
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]
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processor = BaseCPUProcessor(
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cores=cores,
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)
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else:
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processor = SimpleProcessor(
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cpu_type=cpu_enum,
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isa=isa_enum,
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num_cores=args.num_cores,
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)
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if args.riscv_32bits:
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for simple_core in processor.cores:
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for i in range(len(simple_core.core.isa)):
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simple_core.core.isa[i].riscv_type = "RV32"
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motherboard = SimpleBoard(
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clk_freq="3GHz",
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@@ -170,8 +105,10 @@ motherboard = SimpleBoard(
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)
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# Set the workload
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binary = Resource(args.resource, resource_directory=args.resource_directory)
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motherboard.set_se_binary_workload(binary, arguments=args.arguments)
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binary = obtain_resource(
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args.resource, resource_directory=args.resource_directory
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)
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motherboard.set_se_binary_workload(binary)
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# Run the simulation
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simulator = Simulator(board=motherboard)
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@@ -34,7 +34,7 @@ else:
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# The following lists the RISCV binaries. Those commented out presently result
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# in a test failure. This is outlined in the following Jira issue:
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# https://gem5.atlassian.net/browse/GEM5-496
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binaries = (
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rv64_binaries = (
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"rv64samt-ps-sysclone_d",
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"rv64samt-ps-sysfutex1_d",
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# 'rv64samt-ps-sysfutex2_d',
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@@ -69,6 +69,50 @@ binaries = (
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"rv64uamt-ps-amoswap_d",
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"rv64uamt-ps-amoxor_d",
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"rv64uamt-ps-lrsc_d",
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"rv64ub-ps-add_uw",
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"rv64ub-ps-andn",
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"rv64ub-ps-bclr",
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"rv64ub-ps-bclri",
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"rv64ub-ps-bext",
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"rv64ub-ps-bexti",
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"rv64ub-ps-binv",
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"rv64ub-ps-binvi",
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"rv64ub-ps-bset",
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"rv64ub-ps-bseti",
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"rv64ub-ps-clmul",
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"rv64ub-ps-clmulh",
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"rv64ub-ps-clmulr",
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"rv64ub-ps-clz",
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"rv64ub-ps-clzw",
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"rv64ub-ps-cpop",
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"rv64ub-ps-cpopw",
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"rv64ub-ps-ctz",
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"rv64ub-ps-ctzw",
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"rv64ub-ps-max",
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"rv64ub-ps-maxu",
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"rv64ub-ps-min",
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"rv64ub-ps-minu",
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"rv64ub-ps-orc_b",
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"rv64ub-ps-orn",
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"rv64ub-ps-rev8",
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"rv64ub-ps-rol",
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"rv64ub-ps-rolw",
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"rv64ub-ps-ror",
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"rv64ub-ps-rori",
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"rv64ub-ps-roriw",
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"rv64ub-ps-rorw",
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"rv64ub-ps-sext_b",
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"rv64ub-ps-sext_h",
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"rv64ub-ps-sh1add",
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"rv64ub-ps-sh1add_uw",
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"rv64ub-ps-sh2add",
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"rv64ub-ps-sh2add_uw",
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"rv64ub-ps-sh3add",
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"rv64ub-ps-sh3add_uw",
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"rv64ub-ps-slli_uw",
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"rv64ub-ps-xnor",
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"rv64ub-ps-zext_h",
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"rv64uc-ps-rvc",
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"rv64ud-ps-fadd",
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"rv64ud-ps-fclass",
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"rv64ud-ps-fcmp",
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@@ -169,10 +213,145 @@ binaries = (
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"rv64uzfh-ps-recoding",
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)
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rv32_binaries = (
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"rv32ua-ps-amoadd_w",
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"rv32ua-ps-amoand_w",
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"rv32ua-ps-amomaxu_w",
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"rv32ua-ps-amomax_w",
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"rv32ua-ps-amominu_w",
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"rv32ua-ps-amomin_w",
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"rv32ua-ps-amoor_w",
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"rv32ua-ps-amoswap_w",
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"rv32ua-ps-amoxor_w",
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"rv32ua-ps-lrsc",
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"rv32uamt-ps-amoadd_w",
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"rv32uamt-ps-amoand_w",
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"rv32uamt-ps-amomaxu_w",
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"rv32uamt-ps-amomax_w",
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"rv32uamt-ps-amominu_w",
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"rv32uamt-ps-amomin_w",
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"rv32uamt-ps-amoor_w",
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"rv32uamt-ps-amoswap_w",
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"rv32uamt-ps-amoxor_w",
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"rv32uamt-ps-lrsc_w",
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"rv32ub-ps-andn",
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"rv32ub-ps-bclr",
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"rv32ub-ps-bclri",
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"rv32ub-ps-bext",
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"rv32ub-ps-bexti",
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"rv32ub-ps-binv",
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"rv32ub-ps-binvi",
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"rv32ub-ps-bset",
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"rv32ub-ps-bseti",
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"rv32ub-ps-clmul",
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"rv32ub-ps-clmulh",
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"rv32ub-ps-clmulr",
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"rv32ub-ps-clz",
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"rv32ub-ps-cpop",
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"rv32ub-ps-ctz",
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"rv32ub-ps-max",
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"rv32ub-ps-maxu",
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"rv32ub-ps-min",
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"rv32ub-ps-minu",
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"rv32ub-ps-orc_b",
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"rv32ub-ps-orn",
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"rv32ub-ps-rev8",
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"rv32ub-ps-rol",
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"rv32ub-ps-ror",
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"rv32ub-ps-rori",
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"rv32ub-ps-sext_b",
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"rv32ub-ps-sext_h",
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"rv32ub-ps-sh1add",
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"rv32ub-ps-sh2add",
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"rv32ub-ps-sh3add",
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"rv32ub-ps-xnor",
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"rv32ub-ps-zext_h",
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"rv32uc-ps-rvc",
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"rv32ud-ps-fadd",
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"rv32ud-ps-fclass",
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"rv32ud-ps-fcmp",
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"rv32ud-ps-fcvt",
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"rv32ud-ps-fcvt_w",
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"rv32ud-ps-fdiv",
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"rv32ud-ps-fmadd",
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"rv32ud-ps-fmin",
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"rv32ud-ps-ldst",
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"rv32ud-ps-recoding",
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"rv32uf-ps-fadd",
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"rv32uf-ps-fclass",
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"rv32uf-ps-fcmp",
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"rv32uf-ps-fcvt",
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"rv32uf-ps-fcvt_w",
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"rv32uf-ps-fdiv",
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"rv32uf-ps-fmadd",
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"rv32uf-ps-fmin",
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"rv32uf-ps-ldst",
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"rv32uf-ps-move",
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"rv32uf-ps-recoding",
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"rv32ui-ps-add",
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"rv32ui-ps-addi",
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"rv32ui-ps-and",
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"rv32ui-ps-andi",
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"rv32ui-ps-auipc",
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"rv32ui-ps-beq",
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"rv32ui-ps-bge",
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"rv32ui-ps-bgeu",
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"rv32ui-ps-blt",
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"rv32ui-ps-bltu",
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"rv32ui-ps-bne",
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"rv32ui-ps-fence_i",
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"rv32ui-ps-jal",
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"rv32ui-ps-jalr",
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"rv32ui-ps-lb",
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"rv32ui-ps-lbu",
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"rv32ui-ps-lh",
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"rv32ui-ps-lhu",
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"rv32ui-ps-lui",
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"rv32ui-ps-lw",
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"rv32ui-ps-or",
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"rv32ui-ps-ori",
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"rv32ui-ps-sb",
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"rv32ui-ps-sh",
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"rv32ui-ps-simple",
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"rv32ui-ps-sll",
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"rv32ui-ps-slli",
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"rv32ui-ps-slt",
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"rv32ui-ps-slti",
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"rv32ui-ps-sltiu",
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"rv32ui-ps-sltu",
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"rv32ui-ps-sra",
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"rv32ui-ps-srai",
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"rv32ui-ps-srl",
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"rv32ui-ps-srli",
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"rv32ui-ps-sub",
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"rv32ui-ps-sw",
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"rv32ui-ps-xor",
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"rv32ui-ps-xori",
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"rv32um-ps-div",
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"rv32um-ps-divu",
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"rv32um-ps-mul",
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"rv32um-ps-mulh",
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"rv32um-ps-mulhsu",
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"rv32um-ps-mulhu",
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"rv32um-ps-rem",
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"rv32um-ps-remu",
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"rv32uzfh-ps-fadd",
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"rv32uzfh-ps-fclass",
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"rv32uzfh-ps-fcmp",
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"rv32uzfh-ps-fcvt",
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"rv32uzfh-ps-fcvt_w",
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"rv32uzfh-ps-fdiv",
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"rv32uzfh-ps-fmadd",
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"rv32uzfh-ps-fmin",
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"rv32uzfh-ps-ldst",
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"rv32uzfh-ps-move",
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"rv32uzfh-ps-recoding",
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)
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cpu_types = ("atomic", "timing", "minor", "o3")
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for cpu_type in cpu_types:
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for binary in binaries:
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for binary in rv64_binaries:
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gem5_verify_config(
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name=f"asm-riscv-{binary}-{cpu_type}",
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verifiers=(),
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@@ -182,12 +361,11 @@ for cpu_type in cpu_types:
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"gem5",
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"asmtest",
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"configs",
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"simple_binary_run.py",
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"riscv_asmtest.py",
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),
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config_args=[
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binary,
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cpu_type,
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"riscv",
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"--num-cores",
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"4",
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"--resource-directory",
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@@ -196,3 +374,27 @@ for cpu_type in cpu_types:
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valid_isas=(constants.all_compiled_tag,),
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valid_hosts=constants.supported_hosts,
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)
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for binary in rv32_binaries:
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gem5_verify_config(
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name=f"asm-riscv-{binary}-{cpu_type}",
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verifiers=(),
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config=joinpath(
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config.base_dir,
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"tests",
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"gem5",
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"asmtest",
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"configs",
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"riscv_asmtest.py",
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),
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config_args=[
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binary,
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cpu_type,
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"--num-cores",
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"4",
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"--riscv-32bits",
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"--resource-directory",
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resource_path,
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],
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valid_isas=(constants.all_compiled_tag,),
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valid_hosts=constants.supported_hosts,
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)
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Block a user