diff --git a/tests/gem5/asmtest/configs/simple_binary_run.py b/tests/gem5/asmtest/configs/riscv_asmtest.py similarity index 58% rename from tests/gem5/asmtest/configs/simple_binary_run.py rename to tests/gem5/asmtest/configs/riscv_asmtest.py index 5540e806ba..e98ec1bd49 100644 --- a/tests/gem5/asmtest/configs/simple_binary_run.py +++ b/tests/gem5/asmtest/configs/riscv_asmtest.py @@ -31,7 +31,7 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in gem5 while still being functinal. """ -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.components.processors.cpu_types import ( get_cpu_types_str_set, get_cpu_type_from_str, @@ -40,29 +40,13 @@ from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.no_cache import NoCache from gem5.components.processors.simple_processor import SimpleProcessor -from gem5.components.processors.base_cpu_core import BaseCPUCore -from gem5.components.processors.base_cpu_processor import BaseCPUProcessor -from gem5.components.processors.simple_core import SimpleCore -from gem5.components.boards.mem_mode import MemMode -from gem5.components.processors.cpu_types import CPUTypes from gem5.simulate.simulator import Simulator -from gem5.isas import get_isa_from_str, get_isas_str_set, ISA - -from m5.util import fatal +from gem5.isas import ISA import argparse -import importlib - -cpu_types_string_map = { - CPUTypes.ATOMIC: "AtomicSimpleCPU", - CPUTypes.O3: "O3CPU", - CPUTypes.TIMING: "TimingSimpleCPU", - CPUTypes.KVM: "KvmCPU", - CPUTypes.MINOR: "MinorCPU", -} parser = argparse.ArgumentParser( - description="A gem5 script for running simple binaries in SE mode." + description="A gem5 script for testing RISC-V instructions" ) parser.add_argument( @@ -73,17 +57,6 @@ parser.add_argument( "cpu", type=str, choices=get_cpu_types_str_set(), help="The CPU type used." ) -parser.add_argument( - "isa", type=str, choices=get_isas_str_set(), help="The ISA used" -) - -parser.add_argument( - "-b", - "--base-cpu-processor", - action="store_true", - help="Use the BaseCPUProcessor instead of the SimpleProcessor.", -) - parser.add_argument( "--riscv-32bits", action="store_true", @@ -98,15 +71,6 @@ parser.add_argument( help="The directory in which resources will be downloaded or exist.", ) -parser.add_argument( - "--arguments", - type=str, - action="append", - default=[], - required=False, - help="The input arguments for the binary.", -) - parser.add_argument( "-n", "--num-cores", @@ -122,45 +86,16 @@ args = parser.parse_args() cache_hierarchy = NoCache() memory = SingleChannelDDR3_1600() -isa_enum = get_isa_from_str(args.isa) -cpu_enum = get_cpu_type_from_str(args.cpu) +processor = SimpleProcessor( + cpu_type=get_cpu_type_from_str(args.cpu), + isa=ISA.RISCV, + num_cores=args.num_cores, +) -if isa_enum == ISA.RISCV and args.riscv_32bits and not args.base_cpu_processor: - fatal("To use Riscv 32 CPU, the base_cpu_processor must be specify!") - -if args.base_cpu_processor: - - if isa_enum == ISA.RISCV and args.riscv_32bits: - m5_objects = importlib.import_module("m5.objects") - cpu_class = getattr( - m5_objects, f"Riscv32{cpu_types_string_map[cpu_enum]}" - ) - cores = [ - BaseCPUCore(core=cpu_class(cpu_id=i), isa=isa_enum) - for i in range(args.num_cores) - ] - else: - cores = [ - BaseCPUCore( - core=SimpleCore.cpu_simobject_factory( - cpu_type=cpu_enum, - isa=isa_enum, - core_id=i, - ), - isa=isa_enum, - ) - for i in range(args.num_cores) - ] - - processor = BaseCPUProcessor( - cores=cores, - ) -else: - processor = SimpleProcessor( - cpu_type=cpu_enum, - isa=isa_enum, - num_cores=args.num_cores, - ) +if args.riscv_32bits: + for simple_core in processor.cores: + for i in range(len(simple_core.core.isa)): + simple_core.core.isa[i].riscv_type = "RV32" motherboard = SimpleBoard( clk_freq="3GHz", @@ -170,8 +105,10 @@ motherboard = SimpleBoard( ) # Set the workload -binary = Resource(args.resource, resource_directory=args.resource_directory) -motherboard.set_se_binary_workload(binary, arguments=args.arguments) +binary = obtain_resource( + args.resource, resource_directory=args.resource_directory +) +motherboard.set_se_binary_workload(binary) # Run the simulation simulator = Simulator(board=motherboard) diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py index 02283ec213..62e4ef5859 100644 --- a/tests/gem5/asmtest/tests.py +++ b/tests/gem5/asmtest/tests.py @@ -34,7 +34,7 @@ else: # The following lists the RISCV binaries. Those commented out presently result # in a test failure. This is outlined in the following Jira issue: # https://gem5.atlassian.net/browse/GEM5-496 -binaries = ( +rv64_binaries = ( "rv64samt-ps-sysclone_d", "rv64samt-ps-sysfutex1_d", # 'rv64samt-ps-sysfutex2_d', @@ -69,6 +69,50 @@ binaries = ( "rv64uamt-ps-amoswap_d", "rv64uamt-ps-amoxor_d", "rv64uamt-ps-lrsc_d", + "rv64ub-ps-add_uw", + "rv64ub-ps-andn", + "rv64ub-ps-bclr", + "rv64ub-ps-bclri", + "rv64ub-ps-bext", + "rv64ub-ps-bexti", + "rv64ub-ps-binv", + "rv64ub-ps-binvi", + "rv64ub-ps-bset", + "rv64ub-ps-bseti", + "rv64ub-ps-clmul", + "rv64ub-ps-clmulh", + "rv64ub-ps-clmulr", + "rv64ub-ps-clz", + "rv64ub-ps-clzw", + "rv64ub-ps-cpop", + "rv64ub-ps-cpopw", + "rv64ub-ps-ctz", + "rv64ub-ps-ctzw", + "rv64ub-ps-max", + "rv64ub-ps-maxu", + "rv64ub-ps-min", + "rv64ub-ps-minu", + "rv64ub-ps-orc_b", + "rv64ub-ps-orn", + "rv64ub-ps-rev8", + "rv64ub-ps-rol", + "rv64ub-ps-rolw", + "rv64ub-ps-ror", + "rv64ub-ps-rori", + "rv64ub-ps-roriw", + "rv64ub-ps-rorw", + "rv64ub-ps-sext_b", + "rv64ub-ps-sext_h", + "rv64ub-ps-sh1add", + "rv64ub-ps-sh1add_uw", + "rv64ub-ps-sh2add", + "rv64ub-ps-sh2add_uw", + "rv64ub-ps-sh3add", + "rv64ub-ps-sh3add_uw", + "rv64ub-ps-slli_uw", + "rv64ub-ps-xnor", + "rv64ub-ps-zext_h", + "rv64uc-ps-rvc", "rv64ud-ps-fadd", "rv64ud-ps-fclass", "rv64ud-ps-fcmp", @@ -169,10 +213,145 @@ binaries = ( "rv64uzfh-ps-recoding", ) +rv32_binaries = ( + "rv32ua-ps-amoadd_w", + "rv32ua-ps-amoand_w", + "rv32ua-ps-amomaxu_w", + "rv32ua-ps-amomax_w", + "rv32ua-ps-amominu_w", + "rv32ua-ps-amomin_w", + "rv32ua-ps-amoor_w", + "rv32ua-ps-amoswap_w", + "rv32ua-ps-amoxor_w", + "rv32ua-ps-lrsc", + "rv32uamt-ps-amoadd_w", + "rv32uamt-ps-amoand_w", + "rv32uamt-ps-amomaxu_w", + "rv32uamt-ps-amomax_w", + "rv32uamt-ps-amominu_w", + "rv32uamt-ps-amomin_w", + "rv32uamt-ps-amoor_w", + "rv32uamt-ps-amoswap_w", + "rv32uamt-ps-amoxor_w", + "rv32uamt-ps-lrsc_w", + "rv32ub-ps-andn", + "rv32ub-ps-bclr", + "rv32ub-ps-bclri", + "rv32ub-ps-bext", + "rv32ub-ps-bexti", + "rv32ub-ps-binv", + "rv32ub-ps-binvi", + "rv32ub-ps-bset", + "rv32ub-ps-bseti", + "rv32ub-ps-clmul", + "rv32ub-ps-clmulh", + "rv32ub-ps-clmulr", + "rv32ub-ps-clz", + "rv32ub-ps-cpop", + "rv32ub-ps-ctz", + "rv32ub-ps-max", + "rv32ub-ps-maxu", + "rv32ub-ps-min", + "rv32ub-ps-minu", + "rv32ub-ps-orc_b", + "rv32ub-ps-orn", + "rv32ub-ps-rev8", + "rv32ub-ps-rol", + "rv32ub-ps-ror", + "rv32ub-ps-rori", + "rv32ub-ps-sext_b", + "rv32ub-ps-sext_h", + "rv32ub-ps-sh1add", + "rv32ub-ps-sh2add", + "rv32ub-ps-sh3add", + "rv32ub-ps-xnor", + "rv32ub-ps-zext_h", + "rv32uc-ps-rvc", + "rv32ud-ps-fadd", + "rv32ud-ps-fclass", + "rv32ud-ps-fcmp", + "rv32ud-ps-fcvt", + "rv32ud-ps-fcvt_w", + "rv32ud-ps-fdiv", + "rv32ud-ps-fmadd", + "rv32ud-ps-fmin", + "rv32ud-ps-ldst", + "rv32ud-ps-recoding", + "rv32uf-ps-fadd", + "rv32uf-ps-fclass", + "rv32uf-ps-fcmp", + "rv32uf-ps-fcvt", + "rv32uf-ps-fcvt_w", + "rv32uf-ps-fdiv", + "rv32uf-ps-fmadd", + "rv32uf-ps-fmin", + "rv32uf-ps-ldst", + "rv32uf-ps-move", + "rv32uf-ps-recoding", + "rv32ui-ps-add", + "rv32ui-ps-addi", + "rv32ui-ps-and", + "rv32ui-ps-andi", + "rv32ui-ps-auipc", + "rv32ui-ps-beq", + "rv32ui-ps-bge", + "rv32ui-ps-bgeu", + "rv32ui-ps-blt", + "rv32ui-ps-bltu", + "rv32ui-ps-bne", + "rv32ui-ps-fence_i", + "rv32ui-ps-jal", + "rv32ui-ps-jalr", + "rv32ui-ps-lb", + "rv32ui-ps-lbu", + "rv32ui-ps-lh", + "rv32ui-ps-lhu", + "rv32ui-ps-lui", + "rv32ui-ps-lw", + "rv32ui-ps-or", + "rv32ui-ps-ori", + "rv32ui-ps-sb", + "rv32ui-ps-sh", + "rv32ui-ps-simple", + "rv32ui-ps-sll", + "rv32ui-ps-slli", + "rv32ui-ps-slt", + "rv32ui-ps-slti", + "rv32ui-ps-sltiu", + "rv32ui-ps-sltu", + "rv32ui-ps-sra", + "rv32ui-ps-srai", + "rv32ui-ps-srl", + "rv32ui-ps-srli", + "rv32ui-ps-sub", + "rv32ui-ps-sw", + "rv32ui-ps-xor", + "rv32ui-ps-xori", + "rv32um-ps-div", + "rv32um-ps-divu", + "rv32um-ps-mul", + "rv32um-ps-mulh", + "rv32um-ps-mulhsu", + "rv32um-ps-mulhu", + "rv32um-ps-rem", + "rv32um-ps-remu", + "rv32uzfh-ps-fadd", + "rv32uzfh-ps-fclass", + "rv32uzfh-ps-fcmp", + "rv32uzfh-ps-fcvt", + "rv32uzfh-ps-fcvt_w", + "rv32uzfh-ps-fdiv", + "rv32uzfh-ps-fmadd", + "rv32uzfh-ps-fmin", + "rv32uzfh-ps-ldst", + "rv32uzfh-ps-move", + "rv32uzfh-ps-recoding", +) + cpu_types = ("atomic", "timing", "minor", "o3") for cpu_type in cpu_types: - for binary in binaries: + for binary in rv64_binaries: gem5_verify_config( name=f"asm-riscv-{binary}-{cpu_type}", verifiers=(), @@ -182,12 +361,11 @@ for cpu_type in cpu_types: "gem5", "asmtest", "configs", - "simple_binary_run.py", + "riscv_asmtest.py", ), config_args=[ binary, cpu_type, - "riscv", "--num-cores", "4", "--resource-directory", @@ -196,3 +374,27 @@ for cpu_type in cpu_types: valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, ) + for binary in rv32_binaries: + gem5_verify_config( + name=f"asm-riscv-{binary}-{cpu_type}", + verifiers=(), + config=joinpath( + config.base_dir, + "tests", + "gem5", + "asmtest", + "configs", + "riscv_asmtest.py", + ), + config_args=[ + binary, + cpu_type, + "--num-cores", + "4", + "--riscv-32bits", + "--resource-directory", + resource_path, + ], + valid_isas=(constants.all_compiled_tag,), + valid_hosts=constants.supported_hosts, + )