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arch-x86: In the LVT in the local APIC, start with all entries masked.

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This is what the APIC is supposed to look like when coming out of reset.

Change-Id: Ia9b6e13533692109849e729d9ad3b358f36e2e47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55451
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2022-01-11 02:33:24 -08:00
parent 7b01dbd926
commit c17d68f739
1 changed files with 13 additions and 0 deletions
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13
src/arch/x86/interrupts.cc
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@@ -616,6 +616,19 @@ X86ISA::Interrupts::Interrupts(const Params &p)
ISRV = 0;
IRRV = 0;
// At reset, all LVT entries start out zeroed, except for their mask bit.
LVTEntry masked = 0;
masked.masked = 1;
regs[APIC_LVT_TIMER] = masked;
regs[APIC_LVT_THERMAL_SENSOR] = masked;
regs[APIC_LVT_PERFORMANCE_MONITORING_COUNTERS] = masked;
regs[APIC_LVT_LINT0] = masked;
regs[APIC_LVT_LINT1] = masked;
regs[APIC_LVT_ERROR] = masked;
regs[APIC_SPURIOUS_INTERRUPT_VECTOR] = 0xff;
regs[APIC_VERSION] = (5 << 16) | 0x14;
}