From c17d68f739f94cfe0531874a3fcb80c7a4199b78 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 11 Jan 2022 02:33:24 -0800 Subject: [PATCH] arch-x86: In the LVT in the local APIC, start with all entries masked. This is what the APIC is supposed to look like when coming out of reset. Change-Id: Ia9b6e13533692109849e729d9ad3b358f36e2e47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55451 Reviewed-by: Matt Sinclair Reviewed-by: Gabe Black Maintainer: Matt Sinclair Tested-by: kokoro --- src/arch/x86/interrupts.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index 80ed3a6460..8499bfbbfa 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -616,6 +616,19 @@ X86ISA::Interrupts::Interrupts(const Params &p) ISRV = 0; IRRV = 0; + // At reset, all LVT entries start out zeroed, except for their mask bit. + LVTEntry masked = 0; + masked.masked = 1; + + regs[APIC_LVT_TIMER] = masked; + regs[APIC_LVT_THERMAL_SENSOR] = masked; + regs[APIC_LVT_PERFORMANCE_MONITORING_COUNTERS] = masked; + regs[APIC_LVT_LINT0] = masked; + regs[APIC_LVT_LINT1] = masked; + regs[APIC_LVT_ERROR] = masked; + + regs[APIC_SPURIOUS_INTERRUPT_VECTOR] = 0xff; + regs[APIC_VERSION] = (5 << 16) | 0x14; }