tests, configs, util, mem, python, systemc: Change base 10 units to base 2 (#1605)

This commit changes metric units (e.g. kB, MB, and GB) to binary units
(KiB, MiB, GiB) in various files. This PR covers files that were missed
by a previous PR that also made these changes.

configs/common/Caches.py

@@ -84,7 +84,7 @@ class IOCache(Cache):
     data_latency = 50
     response_latency = 50
     mshrs = 20
-    size = "1kB"
+    size = "1KiB"
     tgts_per_mshr = 12
 
 
@@ -94,6 +94,6 @@ class PageTableWalkerCache(Cache):
     data_latency = 2
     response_latency = 2
     mshrs = 10
-    size = "1kB"
+    size = "1KiB"
     tgts_per_mshr = 12
     is_read_only = False

configs/common/Options.py

@@ -155,7 +155,7 @@ def addNoISAOptions(parser):
         "--mem-size",
         action="store",
         type=str,
-        default="512MB",
+        default="512MiB",
         help="Specify the physical memory size (single memory)",
     )
     parser.add_argument(
@@ -188,10 +188,10 @@ def addNoISAOptions(parser):
     parser.add_argument("--num-dirs", type=int, default=1)
     parser.add_argument("--num-l2caches", type=int, default=1)
     parser.add_argument("--num-l3caches", type=int, default=1)
-    parser.add_argument("--l1d_size", type=str, default="64kB")
-    parser.add_argument("--l1i_size", type=str, default="32kB")
-    parser.add_argument("--l2_size", type=str, default="2MB")
-    parser.add_argument("--l3_size", type=str, default="16MB")
+    parser.add_argument("--l1d_size", type=str, default="64KiB")
+    parser.add_argument("--l1i_size", type=str, default="32KiB")
+    parser.add_argument("--l2_size", type=str, default="2MiB")
+    parser.add_argument("--l3_size", type=str, default="16MiB")
     parser.add_argument("--l1d_assoc", type=int, default=2)
     parser.add_argument("--l1i_assoc", type=int, default=2)
     parser.add_argument("--l2_assoc", type=int, default=8)

configs/common/cores/arm/HPI.py

@@ -1704,7 +1704,7 @@ class HPI_ICache(Cache):
     response_latency = 1
     mshrs = 2
     tgts_per_mshr = 8
-    size = "32kB"
+    size = "32KiB"
     assoc = 2
     # No prefetcher, this is handled by the core
 
@@ -1715,7 +1715,7 @@ class HPI_DCache(Cache):
     response_latency = 1
     mshrs = 4
     tgts_per_mshr = 8
-    size = "32kB"
+    size = "32KiB"
     assoc = 4
     write_buffers = 4
     prefetcher = StridePrefetcher(queue_size=4, degree=4)
@@ -1727,7 +1727,7 @@ class HPI_L2(Cache):
     response_latency = 5
     mshrs = 4
     tgts_per_mshr = 8
-    size = "1024kB"
+    size = "1024KiB"
     assoc = 16
     write_buffers = 16
     # prefetcher FIXME

configs/common/cores/arm/O3_ARM_v7a.py

@@ -176,7 +176,7 @@ class O3_ARM_v7a_ICache(Cache):
     response_latency = 1
     mshrs = 2
     tgts_per_mshr = 8
-    size = "32kB"
+    size = "32KiB"
     assoc = 2
     is_read_only = True
     # Writeback clean lines as well
@@ -190,7 +190,7 @@ class O3_ARM_v7a_DCache(Cache):
     response_latency = 2
     mshrs = 6
     tgts_per_mshr = 8
-    size = "32kB"
+    size = "32KiB"
     assoc = 2
     write_buffers = 16
     # Consider the L2 a victim cache also for clean lines
@@ -204,7 +204,7 @@ class O3_ARM_v7aL2(Cache):
     response_latency = 12
     mshrs = 16
     tgts_per_mshr = 8
-    size = "1MB"
+    size = "1MiB"
     assoc = 16
     write_buffers = 8
     clusivity = "mostly_excl"

configs/common/cores/arm/ex5_LITTLE.py

@@ -124,7 +124,7 @@ class L1Cache(Cache):
 
 class L1I(L1Cache):
     mshrs = 2
-    size = "32kB"
+    size = "32KiB"
     assoc = 2
     is_read_only = True
     tgts_per_mshr = 20
@@ -132,7 +132,7 @@ class L1I(L1Cache):
 
 class L1D(L1Cache):
     mshrs = 4
-    size = "32kB"
+    size = "32KiB"
     assoc = 4
     write_buffers = 4
 
@@ -144,7 +144,7 @@ class L2(Cache):
     response_latency = 9
     mshrs = 8
     tgts_per_mshr = 12
-    size = "512kB"
+    size = "512KiB"
     assoc = 8
     write_buffers = 16
     clusivity = "mostly_excl"

configs/common/cores/arm/ex5_big.py

@@ -177,7 +177,7 @@ class L1Cache(Cache):
 # Instruction Cache
 class L1I(L1Cache):
     mshrs = 2
-    size = "32kB"
+    size = "32KiB"
     assoc = 2
     is_read_only = True
 
@@ -185,7 +185,7 @@ class L1I(L1Cache):
 # Data Cache
 class L1D(L1Cache):
     mshrs = 6
-    size = "32kB"
+    size = "32KiB"
     assoc = 2
     write_buffers = 16
 
@@ -197,7 +197,7 @@ class L2(Cache):
     response_latency = 15
     mshrs = 16
     tgts_per_mshr = 8
-    size = "2MB"
+    size = "2MiB"
     assoc = 16
     write_buffers = 8
     clusivity = "mostly_excl"

configs/example/arm/starter_fs.py

@@ -276,7 +276,7 @@ def main():
         "--mem-size",
         action="store",
         type=str,
-        default="2GB",
+        default="2GiB",
         help="Specify the physical memory size",
     )
     parser.add_argument(

configs/example/gpufs/hip_cookbook.py

@@ -128,8 +128,8 @@ if __name__ == "__m5_main__":
     args.num_cpus = 1
     args.mem_size = "3GiB"
     args.dgpu = True
-    args.dgpu_mem_size = "16GB"
-    args.dgpu_start = "0GB"
+    args.dgpu_mem_size = "16GiB"
+    args.dgpu_start = "0GiB"
     args.checkpoint_restore = 0
     args.disjoint = True
     args.timing_gpu = True

configs/example/gpufs/hip_rodinia.py

@@ -136,8 +136,8 @@ if __name__ == "__m5_main__":
     args.num_cpus = 1
     args.mem_size = "3GiB"
     args.dgpu = True
-    args.dgpu_mem_size = "16GB"
-    args.dgpu_start = "0GB"
+    args.dgpu_mem_size = "16GiB"
+    args.dgpu_start = "0GiB"
     args.checkpoint_restore = 0
     args.disjoint = True
     args.timing_gpu = True

configs/example/gpufs/hip_samples.py

@@ -126,8 +126,8 @@ if __name__ == "__m5_main__":
     args.num_cpus = 1
     args.mem_size = "3GiB"
     args.dgpu = True
-    args.dgpu_mem_size = "16GB"
-    args.dgpu_start = "0GB"
+    args.dgpu_mem_size = "16GiB"
+    args.dgpu_start = "0GiB"
     args.checkpoint_restore = 0
     args.disjoint = True
     args.timing_gpu = True

configs/example/gpufs/mi200.py

@@ -142,8 +142,8 @@ def runMI200GPUFS(cpu_type):
     args.cpu_type = "X86KvmCPU"
     args.mem_size = "8GiB"  # CPU host memory
     args.dgpu = True
-    args.dgpu_mem_size = "16GB"  # GPU device memory
-    args.dgpu_start = "0GB"
+    args.dgpu_mem_size = "16GiB"  # GPU device memory
+    args.dgpu_start = "0GiB"
     args.checkpoint_restore = 0
     args.disjoint = True
     args.timing_gpu = True

configs/example/gpufs/mi300.py

@@ -156,7 +156,7 @@ def runMI300GPUFS(
 
     # Defaults for MI300X
     args.gpu_device = "MI300X"
-    args.dgpu_mem_size = "16GB"  # GPU memory size, must be 16GB currently.
+    args.dgpu_mem_size = "16GiB"  # GPU memory size, must be 16GiB currently.
 
     # See: https://rocm.docs.amd.com/en/latest/conceptual/gpu-arch/mi300.html
     # Topology for one XCD. Number of CUs is approximately 304 / 8, rounded

configs/example/gpufs/runfs.py

@@ -112,7 +112,7 @@ def addRunFSOptions(parser):
         "--dgpu-mem-size",
         action="store",
         type=str,
-        default="16GB",
+        default="16GiB",
         help="Specify the dGPU physical memory size",
     )
     parser.add_argument(

configs/example/gpufs/vega10.py

@@ -143,8 +143,8 @@ def runVegaGPUFS(cpu_type):
     args.num_cpus = 1
     args.mem_size = "3GiB"
     args.dgpu = True
-    args.dgpu_mem_size = "16GB"
-    args.dgpu_start = "0GB"
+    args.dgpu_mem_size = "16GiB"
+    args.dgpu_start = "0GiB"
     args.checkpoint_restore = 0
     args.disjoint = True
     args.timing_gpu = True

configs/example/hmctest.py

@@ -60,12 +60,12 @@ def add_options(parser):
     )
 
 
-# considering 4GB HMC device with following parameters
-# hmc_device_size = '4GB'
-# hmc_vault_size = '256MB'
+# considering 4GiB HMC device with following parameters
+# hmc_device_size = '4GiB'
+# hmc_vault_size = '256MiB'
 # hmc_stack_size = 8
 # hmc_bank_in_stack = 2
-# hmc_bank_size = '16MB'
+# hmc_bank_size = '16MiB'
 # hmc_bank_in_vault = 16
 def build_system(options):
     # create the system we are going to simulate

configs/example/ruby_gpu_random_test.py

@@ -122,12 +122,12 @@ args = parser.parse_args()
 if args.cache_size == "small":
     args.tcp_size = "256B"
     args.tcp_assoc = 2
-    args.tcc_size = "1kB"
+    args.tcc_size = "1KiB"
     args.tcc_assoc = 2
 elif args.cache_size == "large":
-    args.tcp_size = "256kB"
+    args.tcp_size = "256KiB"
     args.tcp_assoc = 16
-    args.tcc_size = "1024kB"
+    args.tcc_size = "1024KiB"
     args.tcc_assoc = 16
 
 #

configs/example/ruby_mem_test.py

@@ -91,7 +91,7 @@ args = parser.parse_args()
 args.l1d_size = "256B"
 args.l1i_size = "256B"
 args.l2_size = "512B"
-args.l3_size = "1kB"
+args.l3_size = "1KiB"
 args.l1d_assoc = 2
 args.l1i_assoc = 2
 args.l2_assoc = 2

configs/example/ruby_random_test.py

@@ -80,7 +80,7 @@ args = parser.parse_args()
 args.l1d_size = "256B"
 args.l1i_size = "256B"
 args.l2_size = "512B"
-args.l3_size = "1kB"
+args.l3_size = "1KiB"
 args.l1d_assoc = 2
 args.l1i_assoc = 2
 args.l2_assoc = 2

src/mem/ruby/protocol/GPU_VIPER-SQC.sm

@@ -37,7 +37,7 @@ machine(MachineType:SQC, "GPU SQC (L1 I Cache)")
    CacheMemory * L1cache;
    int TCC_select_num_bits;
    Cycles issue_latency := 80;  // time to send data down to TCC
-   Cycles l2_hit_latency := 18; // for 1MB L2, 20 for 2MB
+   Cycles l2_hit_latency := 18; // for 1MiB L2, 20 for 2MiB
 
   MessageBuffer * requestFromSQC, network="To", virtual_network="1", vnet_type="request";
 

src/python/gem5/resources/md5_utils.py

@@ -38,7 +38,7 @@ def _md5_update_from_file(
     if filename.stat().st_size < 1024 * 1024 * 100:
         from ..utils.progress_bar import FakeTQDM
 
-        # if the file is less than 100MB, no need to show a progress bar.
+        # if the file is less than 100MiB, no need to show a progress bar.
         tqdm = FakeTQDM()
     else:
         from ..utils.progress_bar import tqdm

src/systemc/tests/tlm/endian_conv/testall.py

@@ -62,8 +62,8 @@ words, where N is the length in words
 enables to suppress the part where the other segment is active
 
 Data buffer definition:  starts at 0, randomly filled
-with lower case letters and numbers.  Size 2 kB.  Addresses are limited to
-1 kB.
+with lower case letters and numbers.  Size 2 KiB.  Addresses are limited to
+1 KiB.
 """
 
 

tests/gem5/arm_boot_tests/configs/arm_boot_exit_run.py

@@ -135,7 +135,7 @@ elif args.mem_system == "chi":
     )
 
     cache_hierarchy = PrivateL1CacheHierarchy(
-        size="16kB",
+        size="16KiB",
         assoc=4,
     )
 
@@ -146,11 +146,11 @@ elif args.mem_system == "mesi_two_level":
     )
 
     cache_hierarchy = MESITwoLevelCacheHierarchy(
-        l1d_size="32kB",
+        l1d_size="32KiB",
         l1d_assoc=8,
-        l1i_size="32kB",
+        l1i_size="32KiB",
         l1i_assoc=8,
-        l2_size="256kB",
+        l2_size="256KiB",
         l2_assoc=16,
         num_l2_banks=2,
     )
@@ -161,7 +161,7 @@ elif args.mem_system == "mi_example":
         MIExampleCacheHierarchy,
     )
 
-    cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=4)
+    cache_hierarchy = MIExampleCacheHierarchy(size="32KiB", assoc=4)
 else:
     raise NotImplementedError(
         f"Memory type '{args.mem_system}' is not supported in the boot tests."

tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py

@@ -55,11 +55,11 @@ requires(isa_required=ISA.X86)
 # For classic, PrivateL1PrivateL2 and NoCache have been tested.
 # For Ruby, MESI_Two_Level and MI_example have been tested.
 cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
-    l1d_size="32kB", l1i_size="32kB", l2_size="512kB"
+    l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
 )
 
 # Setup the system memory.
-memory = SingleChannelDDR3_1600(size="1GB")
+memory = SingleChannelDDR3_1600(size="1GiB")
 
 # Setup a single core Processor.
 processor = SimpleProcessor(cpu_type=CPUTypes.O3, isa=ISA.X86, num_cores=1)

tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py

@@ -64,11 +64,11 @@ requires(isa_required=ISA.X86)
 # For classic, PrivateL1PrivateL2 and NoCache have been tested.
 # For Ruby, MESI_Two_Level and MI_example have been tested.
 cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
-    l1d_size="32kB", l1i_size="32kB", l2_size="512kB"
+    l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
 )
 
 # Setup the system memory.
-memory = SingleChannelDDR3_1600(size="1GB")
+memory = SingleChannelDDR3_1600(size="1GiB")
 
 # Setup a single core Processor.
 processor = SimpleProcessor(cpu_type=CPUTypes.O3, isa=ISA.X86, num_cores=1)

tests/gem5/cpu_tests/run.py

@@ -55,7 +55,7 @@ class L1ICache(L1Cache):
     """Simple L1 instruction cache with default values"""
 
     # Set the default size
-    size = "32kB"
+    size = "32KiB"
 
     def connectCPU(self, cpu):
         """Connect this cache's port to a CPU icache port"""
@@ -66,7 +66,7 @@ class L1DCache(L1Cache):
     """Simple L1 data cache with default values"""
 
     # Set the default size
-    size = "32kB"
+    size = "32KiB"
 
     def connectCPU(self, cpu):
         """Connect this cache's port to a CPU dcache port"""
@@ -77,7 +77,7 @@ class L2Cache(Cache):
     """Simple L2 Cache with default values"""
 
     # Default parameters
-    size = "512kB"
+    size = "512KiB"
     assoc = 16
     tag_latency = 10
     data_latency = 10
@@ -134,7 +134,7 @@ if args.cpu not in (
 ):
     system.mem_mode = "timing"
 
-system.mem_ranges = [AddrRange("512MB")]
+system.mem_ranges = [AddrRange("512MiB")]
 
 system.cpu = valid_cpu[args.cpu]()
 

tests/gem5/fs/linux/arm/configs/base_caches.py

@@ -81,5 +81,5 @@ class IOCache(Cache):
     data_latency = 50
     response_latency = 50
     mshrs = 20
-    size = "1kB"
+    size = "1KiB"
     tgts_per_mshr = 12

tests/gem5/fs/linux/arm/configs/base_config.py

@@ -114,7 +114,7 @@ class BaseSystem(metaclass=ABCMeta):
           cpu -- CPU instance to work on.
         """
         cpu.addPrivateSplitL1Caches(
-            L1_ICache(size="32kB", assoc=1), L1_DCache(size="32kB", assoc=4)
+            L1_ICache(size="32KiB", assoc=1), L1_DCache(size="32KiB", assoc=4)
         )
 
     def create_caches_shared(self, system):
@@ -128,7 +128,7 @@ class BaseSystem(metaclass=ABCMeta):
         """
         system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
         system.l2c = L2Cache(
-            clk_domain=system.cpu_clk_domain, size="4MB", assoc=8
+            clk_domain=system.cpu_clk_domain, size="4MiB", assoc=8
         )
         system.l2c.cpu_side = system.toL2Bus.mem_side_ports
         system.l2c.mem_side = system.membus.cpu_side_ports
@@ -197,9 +197,9 @@ class BaseSystem(metaclass=ABCMeta):
 
             # Set the default cache size and associativity to be very
             # small to encourage races between requests and writebacks.
-            args.l1d_size = "32kB"
-            args.l1i_size = "32kB"
-            args.l2_size = "4MB"
+            args.l1d_size = "3KiB"
+            args.l1i_size = "32KiB"
+            args.l2_size = "4MiB"
             args.l1d_assoc = 4
             args.l1i_assoc = 2
             args.l2_assoc = 8
@@ -305,9 +305,9 @@ class BaseSESystemUniprocessor(BaseSESystem):
         if self.mem_mode == "timing":
             # @todo We might want to revisit these rather enthusiastic L1 sizes
             cpu.addTwoLevelCacheHierarchy(
-                L1_ICache(size="128kB"),
-                L1_DCache(size="256kB"),
-                L2Cache(size="2MB"),
+                L1_ICache(size="128KiB"),
+                L1_DCache(size="256KiB"),
+                L2Cache(size="2MiB"),
             )
 
     def create_caches_shared(self, system):
@@ -367,9 +367,9 @@ class BaseFSSystemUniprocessor(BaseFSSystem):
 
     def create_caches_private(self, cpu):
         cpu.addTwoLevelCacheHierarchy(
-            L1_ICache(size="32kB", assoc=1),
-            L1_DCache(size="32kB", assoc=4),
-            L2Cache(size="4MB", assoc=8),
+            L1_ICache(size="32KiB", assoc=1),
+            L1_DCache(size="32KiB", assoc=4),
+            L2Cache(size="4MiB", assoc=8),
         )
 
     def create_caches_shared(self, system):

tests/gem5/gpu/test_gpu_apu_se.py

@@ -108,7 +108,7 @@ gem5_verify_config(
         resource_path,
         "--reg-alloc-policy=dynamic",
         "-n3",
-        "--mem-size=8GB",
+        "--mem-size=8GiB",
         "--dgpu",
         "--gfx-version",
         "gfx900",

tests/gem5/kvm_fork_tests/configs/boot_kvm_fork_run.py

@@ -128,18 +128,18 @@ if args.mem_system == "mi_example":
         MIExampleCacheHierarchy,
     )
 
-    cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=8)
+    cache_hierarchy = MIExampleCacheHierarchy(size="32KiB", assoc=8)
 elif args.mem_system == "mesi_two_level":
     from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
         MESITwoLevelCacheHierarchy,
     )
 
     cache_hierarchy = MESITwoLevelCacheHierarchy(
-        l1d_size="16kB",
+        l1d_size="16KiB",
         l1d_assoc=8,
-        l1i_size="16kB",
+        l1i_size="16KiB",
         l1i_assoc=8,
-        l2_size="256kB",
+        l2_size="256KiB",
         l2_assoc=16,
         num_l2_banks=1,
     )
@@ -148,7 +148,9 @@ elif args.mem_system == "classic":
         PrivateL1CacheHierarchy,
     )
 
-    cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
+    cache_hierarchy = PrivateL1CacheHierarchy(
+        l1d_size="16KiB", l1i_size="16KiB"
+    )
 else:
     raise NotImplementedError(
         f"Memory system '{args.mem_system}' is not supported in the boot tests."
@@ -158,7 +160,7 @@ assert cache_hierarchy != None
 
 # Setup the system memory.
 
-memory = SingleChannelDDR3_1600(size="3GB")
+memory = SingleChannelDDR3_1600(size="3GiB")
 
 processor = SimpleSwitchableProcessor(
     starting_core_type=CPUTypes.KVM,

tests/gem5/kvm_switch_tests/configs/boot_kvm_switch_exit.py

@@ -114,18 +114,18 @@ if args.mem_system == "mi_example":
         MIExampleCacheHierarchy,
     )
 
-    cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=8)
+    cache_hierarchy = MIExampleCacheHierarchy(size="32KiB", assoc=8)
 elif args.mem_system == "mesi_two_level":
     from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
         MESITwoLevelCacheHierarchy,
     )
 
     cache_hierarchy = MESITwoLevelCacheHierarchy(
-        l1d_size="16kB",
+        l1d_size="16KiB",
         l1d_assoc=8,
-        l1i_size="16kB",
+        l1i_size="16KiB",
         l1i_assoc=8,
-        l2_size="256kB",
+        l2_size="256KiB",
         l2_assoc=16,
         num_l2_banks=1,
     )
@@ -134,7 +134,9 @@ elif args.mem_system == "classic":
         PrivateL1CacheHierarchy,
     )
 
-    cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
+    cache_hierarchy = PrivateL1CacheHierarchy(
+        l1d_size="16KiB", l1i_size="16KiB"
+    )
 else:
     raise NotImplementedError(
         f"Memory system '{args.mem_system}' is not supported in the boot tests."
@@ -143,7 +145,7 @@ else:
 assert cache_hierarchy != None
 
 # Setup the system memory.
-memory = SingleChannelDDR3_1600(size="3GB")
+memory = SingleChannelDDR3_1600(size="3GiB")
 
 # Setup a Processor.
 processor = SimpleSwitchableProcessor(

tests/gem5/m5threads_test_atomic/atomic_system.py

@@ -48,7 +48,7 @@ root.system.clk_domain = SrcClockDomain()
 root.system.clk_domain.clock = "3GHz"
 root.system.clk_domain.voltage_domain = VoltageDomain()
 root.system.mem_mode = "timing"
-root.system.mem_ranges = [AddrRange("512MB")]
+root.system.mem_ranges = [AddrRange("512MiB")]
 
 if args.cpu_type == "DerivO3CPU":
     root.system.cpu = [

tests/gem5/memory/memtest-run.py

@@ -49,7 +49,7 @@ system.cpu_clk_domain = SrcClockDomain(
 )
 
 system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
-system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, size="64kB", assoc=8)
+system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, size="64KiB", assoc=8)
 system.l2c.cpu_side = system.toL2Bus.mem_side_ports
 
 # connect l2c to membus
@@ -59,7 +59,7 @@ system.l2c.mem_side = system.membus.cpu_side_ports
 for cpu in cpus:
     # All cpus are associated with cpu_clk_domain
     cpu.clk_domain = system.cpu_clk_domain
-    cpu.l1c = L1Cache(size="32kB", assoc=4)
+    cpu.l1c = L1Cache(size="32KiB", assoc=4)
     cpu.l1c.cpu_side = cpu.port
     cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports
 

tests/gem5/memory/test.py

@@ -41,10 +41,10 @@ gem5_verify_config(
 )
 
 simple_mem_params = [
-    ("inf-bandwidth", {"bandwidth": "0GB/s"}),
+    ("inf-bandwidth", {"bandwidth": "0GiB/s"}),
     ("low-latency", {"latency": "1ns"}),
     ("high-latency", {"latency": "1us"}),
-    ("low-bandwidth", {"bandwidth": "1MB/s"}),
+    ("low-bandwidth", {"bandwidth": "1MiB/s"}),
     ("high-var", {"latency_var": "100ns"}),
 ]
 

tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py

@@ -151,7 +151,7 @@ if args.mem_system == "classic":
     )
 
     cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
-        l1d_size="32kB", l1i_size="32kB", l2_size="256kB"
+        l1d_size="32KiB", l1i_size="32KiB", l2_size="256KiB"
     )
 elif args.mem_system == "mesi_two_level":
     from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
@@ -159,17 +159,17 @@ elif args.mem_system == "mesi_two_level":
     )
 
     cache_hierarchy = MESITwoLevelCacheHierarchy(
-        l1i_size="32kB",
+        l1i_size="32KiB",
         l1i_assoc=8,
-        l1d_size="32kB",
+        l1d_size="32KiB",
         l1d_assoc=8,
-        l2_size="256kB",
+        l2_size="256KiB",
         l2_assoc=16,
         num_l2_banks=1,
     )
 
 # Setup the memory system.
-memory = SingleChannelDDR3_1600(size="3GB")
+memory = SingleChannelDDR3_1600(size="3GiB")
 
 roi_type = get_cpu_type_from_str(args.cpu)
 if args.boot_cpu != None:

tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py

@@ -119,11 +119,11 @@ elif args.mem_system == "mesi_two_level":
 
     # Setup the cache hierarchy.
     cache_hierarchy = MESITwoLevelCacheHierarchy(
-        l1d_size="16kB",
+        l1d_size="16KiB",
         l1d_assoc=8,
-        l1i_size="16kB",
+        l1i_size="16KiB",
         l1i_assoc=8,
-        l2_size="256kB",
+        l2_size="256KiB",
         l2_assoc=16,
         num_l2_banks=1,
     )

tests/gem5/suite_tests/configs/suite_run_workload.py

@@ -97,7 +97,7 @@ cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
 )
 
 # Setup the system memory.
-memory = SingleChannelDDR3_1600(size="3GB")
+memory = SingleChannelDDR3_1600(size="3GiB")
 
 
 def get_processor(isa):

tests/gem5/traffic_gen/configs/simple_traffic_run.py

@@ -53,7 +53,7 @@ def generator_factory(
 
         return LinearGenerator(
             duration="250us",
-            rate="40GB/s",
+            rate="40GiB/s",
             num_cores=generator_cores,
             max_addr=mem_size,
         )
@@ -62,7 +62,7 @@ def generator_factory(
 
         return RandomGenerator(
             duration="250us",
-            rate="40GB/s",
+            rate="40GiB/s",
             num_cores=generator_cores,
             max_addr=mem_size,
         )

tests/gem5/x86_boot_tests/configs/x86_boot_exit_run.py

@@ -128,18 +128,18 @@ if args.mem_system == "mi_example":
         MIExampleCacheHierarchy,
     )
 
-    cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=8)
+    cache_hierarchy = MIExampleCacheHierarchy(size="32KiB", assoc=8)
 elif args.mem_system == "mesi_two_level":
     from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
         MESITwoLevelCacheHierarchy,
     )
 
     cache_hierarchy = MESITwoLevelCacheHierarchy(
-        l1d_size="16kB",
+        l1d_size="16KiB",
         l1d_assoc=8,
-        l1i_size="16kB",
+        l1i_size="16KiB",
         l1i_assoc=8,
-        l2_size="256kB",
+        l2_size="256KiB",
         l2_assoc=16,
         num_l2_banks=1,
     )
@@ -148,7 +148,9 @@ elif args.mem_system == "classic":
         PrivateL1CacheHierarchy,
     )
 
-    cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
+    cache_hierarchy = PrivateL1CacheHierarchy(
+        l1d_size="16KiB", l1i_size="16KiB"
+    )
 else:
     raise NotImplementedError(
         f"Memory system '{args.mem_system}' is not supported in the boot tests."
@@ -157,7 +159,7 @@ else:
 assert cache_hierarchy != None
 
 # Setup the system memory.
-# Warning: This must be kept at 3GB for now. X86Motherboard does not support
+# Warning: This must be kept at 3GiB for now. X86Motherboard does not support
 # anything else right now!
 python_module = "gem5.components.memory"
 memory_class = getattr(importlib.import_module(python_module), args.dram_class)

util/gem5img.py

@@ -65,7 +65,7 @@ MaxLBASectors = 63
 MaxLBABlocks = MaxLBACylinders * MaxLBAHeads * MaxLBASectors
 
 BlockSize = 512
-MB = 1024 * 1024
+MiB = 1024 * 1024
 
 # Setup PATH to look in the sbins.
 env["PATH"] += ":/sbin:/usr/sbin"
@@ -77,8 +77,8 @@ debug = False
 # Figure out cylinders, heads and sectors from a size in blocks.
 def chsFromSize(sizeInBlocks):
     if sizeInBlocks >= MaxLBABlocks:
-        sizeInMBs = (sizeInBlocks * BlockSize) / MB
-        print("%d MB is too big for LBA, truncating file." % sizeInMBs)
+        sizeInMiBs = (sizeInBlocks * BlockSize) / MiB
+        print("%d MiB is too big for LBA, truncating file." % sizeInMiBs)
         return (MaxLBACylinders, MaxLBAHeads, MaxLBASectors)
 
     sectors = sizeInBlocks
@@ -285,7 +285,7 @@ class Command:
 initCom = Command(
     "init",
     "Create an image with an empty file system.",
-    [("file", "Name of the image file."), ("mb", "Size of the file in MB.")],
+    [("file", "Name of the image file."), ("mb", "Size of the file in MiB.")],
 )
 initCom.addArgument(
     "-t",
@@ -356,12 +356,12 @@ umountCom.func = umountComFunc
 newCom = Command(
     "new",
     'File creation part of "init".',
-    [("file", "Name of the image file."), ("mb", "Size of the file in MB.")],
+    [("file", "Name of the image file."), ("mb", "Size of the file in MiB.")],
 )
 
 
 def newImage(file, mb):
-    (cylinders, heads, sectors) = chsFromSize((mb * MB) / BlockSize)
+    (cylinders, heads, sectors) = chsFromSize((mb * MiB) / BlockSize)
     size = cylinders * heads * sectors * BlockSize
 
     # We lseek to the end of the file and only write one byte there. This
@@ -463,7 +463,7 @@ def initComFunc(options, args):
     if dev.setup(path) != 0:
         exit(1)
     size = os.path.getsize(path)
-    if partition(dev, *chsFromSize((mb * MB) / BlockSize)) != 0:
+    if partition(dev, *chsFromSize((mb * MiB) / BlockSize)) != 0:
         dev.destroy()
         exit(1)
     dev.destroy()

util/plot_dram/dram_lat_mem_rd_plot.py

@@ -136,9 +136,9 @@ def main():
     xticks_labels = []
     for x in xticks_locations:
         if x < 1024:
-            xticks_labels.append("%d kB" % x)
+            xticks_labels.append("%d KiB" % x)
         else:
-            xticks_labels.append("%d MB" % (x / 1024))
+            xticks_labels.append("%d MiB" % (x / 1024))
     plt.xticks(xticks_locations, xticks_labels, rotation=-45)
 
     plt.minorticks_off()

util/systemc/systemc_within_gem5/systemc_gem5_tlm/config.py

@@ -62,7 +62,7 @@ system.target = TLM_Target()
 system.physmem = (
     SimpleMemory()
 )  # This must be instanciated, even if not needed
-# system.mem.addr_ranges = [AddrRange('512MB')]
+# system.mem.addr_ranges = [AddrRange('512MiB')]
 system.transactor = Gem5ToTlmBridge32()
 system.clk_domain = SrcClockDomain(clock="1.5GHz", voltage_domain=vd)
 

util/tlm/conf/tlm_elastic_slave.py

@@ -42,7 +42,7 @@ from Caches import *
 # This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
 # and an external TLM port for SystemC co-simulation.
 #
-# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
+# We assume a DRAM size of 512MiB and L1 cache sizes of 32KB.
 #
 # Base System Architecture:
 #
@@ -69,7 +69,7 @@ from Caches import *
 system = System(
     cpu=TraceCPU(),
     mem_mode="timing",
-    mem_ranges=[AddrRange("512MB")],
+    mem_ranges=[AddrRange("512MiB")],
     cache_line_size=64,
 )
 
@@ -92,8 +92,8 @@ system.cpu_clk_domain = SrcClockDomain(
 )
 
 # Setup CPU's L1 caches:
-system.cpu.icache = L1_ICache(size="32kB")
-system.cpu.dcache = L1_DCache(size="32kB")
+system.cpu.icache = L1_ICache(size="32KiB")
+system.cpu.dcache = L1_DCache(size="32KiB")
 system.cpu.icache.cpu_side = system.cpu.icache_port
 system.cpu.dcache.cpu_side = system.cpu.dcache_port
 
@@ -109,7 +109,7 @@ system.physmem = (
 
 # Create a external TLM port:
 system.tlm = ExternalSlave()
-system.tlm.addr_ranges = [AddrRange("512MB")]
+system.tlm.addr_ranges = [AddrRange("512MiB")]
 system.tlm.port_type = "tlm_slave"
 system.tlm.port_data = "transactor"
 

util/tlm/conf/tlm_master.py

@@ -51,7 +51,7 @@ from m5.objects import *
 # Create a system with a Crossbar and a simple Memory:
 system = System()
 system.membus = IOXBar(width=16)
-system.physmem = SimpleMemory(range=AddrRange("512MB"))
+system.physmem = SimpleMemory(range=AddrRange("512MiB"))
 system.clk_domain = SrcClockDomain(
     clock="1.5GHz", voltage_domain=VoltageDomain(voltage="1V")
 )

util/tlm/conf/tlm_slave.py

@@ -63,7 +63,7 @@ system.clk_domain = SrcClockDomain(
 
 # Create a external TLM port:
 system.tlm = ExternalSlave()
-system.tlm.addr_ranges = [AddrRange("512MB")]
+system.tlm.addr_ranges = [AddrRange("512MiB")]
 system.tlm.port_type = "tlm_slave"
 system.tlm.port_data = "transactor"
 

util/tlm/examples/tlm_elastic_slave_with_l2.py

@@ -42,8 +42,8 @@ from Caches import *
 # This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
 # and an external TLM port for SystemC co-simulation.
 #
-# We assume a DRAM size of 512MB and L1 cache sizes of 32KB and an L2 cache
-# size of 1MB.
+# We assume a DRAM size of 512MiB and L1 cache sizes of 32KiB and an L2 cache
+# size of 1MiB.
 #
 # Base System Architecture:
 #
@@ -76,7 +76,7 @@ from Caches import *
 system = System(
     cpu=TraceCPU(),
     mem_mode="timing",
-    mem_ranges=[AddrRange("1024MB")],
+    mem_ranges=[AddrRange("1024MiB")],
     cache_line_size=64,
 )
 
@@ -99,8 +99,8 @@ system.cpu_clk_domain = SrcClockDomain(
 )
 
 # Setup CPU's L1 caches:
-system.cpu.icache = L1_ICache(size="32kB")
-system.cpu.dcache = L1_DCache(size="32kB")
+system.cpu.icache = L1_ICache(size="32KiB")
+system.cpu.dcache = L1_DCache(size="32KiB")
 system.cpu.icache.cpu_side = system.cpu.icache_port
 system.cpu.dcache.cpu_side = system.cpu.dcache_port
 
@@ -110,14 +110,14 @@ system.cpu.dataTraceFile = "system.cpu.traceListener.data.gz"
 
 # Setting up L1 BUS:
 system.tol2bus = L2XBar()
-system.l2cache = L2Cache(size="1MB")
+system.l2cache = L2Cache(size="1MiB")
 system.physmem = (
     SimpleMemory()
 )  # This must be instantiated, even if not needed
 
 # Create a external TLM port:
 system.tlm = ExternalSlave()
-system.tlm.addr_ranges = [AddrRange("4096MB")]
+system.tlm.addr_ranges = [AddrRange("4096MiB")]
 system.tlm.port_type = "tlm_slave"
 system.tlm.port_data = "transactor1"