c10feed524
This commit changes metric units (e.g. kB, MB, and GB) to binary units (KiB, MiB, GiB) in various files. This PR covers files that were missed by a previous PR that also made these changes.
178 lines
5.4 KiB
Python
178 lines
5.4 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import argparse
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import os
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import sys
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import addToPath
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addToPath("../")
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from common import Options
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from ruby import Ruby
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# Get paths we might need. It's expected this file is in m5/configs/example.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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parser = argparse.ArgumentParser()
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Options.addNoISAOptions(parser)
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parser.add_argument(
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"--maxloads", metavar="N", default=100, help="Stop after N loads"
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)
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parser.add_argument(
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"-f",
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"--wakeup_freq",
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metavar="N",
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default=10,
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help="Wakeup every N cycles",
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)
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#
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# Add the ruby specific and protocol specific options
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#
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Ruby.define_options(parser)
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exec(
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compile(
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open(os.path.join(config_root, "common", "Options.py")).read(),
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os.path.join(config_root, "common", "Options.py"),
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"exec",
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)
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)
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args = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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args.l1d_size = "256B"
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args.l1i_size = "256B"
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args.l2_size = "512B"
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args.l3_size = "1KiB"
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args.l1d_assoc = 2
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args.l1i_assoc = 2
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args.l2_assoc = 2
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args.l3_assoc = 2
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#
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# Create the ruby random tester
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#
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# Check the protocol
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check_flush = False
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if buildEnv["PROTOCOL"] == "MOESI_hammer":
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check_flush = True
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tester = RubyTester(
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check_flush=check_flush,
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checks_to_complete=args.maxloads,
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wakeup_frequency=args.wakeup_freq,
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)
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#
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# Create the M5 system. Note that the Memory Object isn't
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# actually used by the rubytester, but is included to support the
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# M5 memory size == Ruby memory size checks
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#
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system = System(cpu=tester, mem_ranges=[AddrRange(args.mem_size)])
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# Create a top-level voltage domain and clock domain
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system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
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system.clk_domain = SrcClockDomain(
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clock=args.sys_clock, voltage_domain=system.voltage_domain
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)
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# the ruby tester reuses num_cpus to specify the
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# number of cpu ports connected to the tester object, which
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# is stored in system.cpu. because there is only ever one
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# tester object, num_cpus is not necessarily equal to the
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# size of system.cpu
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cpu_list = [system.cpu] * args.num_cpus
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Ruby.create_system(args, False, system, cpus=cpu_list)
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# Create a seperate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(
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clock=args.ruby_clock, voltage_domain=system.voltage_domain
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)
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assert args.num_cpus == len(system.ruby._cpu_ports)
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tester.num_cpus = len(system.ruby._cpu_ports)
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#
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# The tester is most effective when randomization is turned on and
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# artifical delay is randomly inserted on messages
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#
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system.ruby.randomization = True
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for ruby_port in system.ruby._cpu_ports:
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#
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# Tie the ruby tester ports to the ruby cpu read and write ports
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#
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if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
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tester.cpuInstDataPort = ruby_port.in_ports
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elif ruby_port.support_data_reqs:
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tester.cpuDataPort = ruby_port.in_ports
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elif ruby_port.support_inst_reqs:
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tester.cpuInstPort = ruby_port.in_ports
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# Do not automatically retry stalled Ruby requests
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ruby_port.no_retry_on_stall = True
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#
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# Tell each sequencer this is the ruby tester so that it
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# copies the subblock back to the checker
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#
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ruby_port.using_ruby_tester = True
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# -----------------------
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# run simulation
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# -----------------------
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root = Root(full_system=False, system=system)
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root.system.mem_mode = "timing"
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency("1ns")
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# instantiate configuration
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m5.instantiate()
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# simulate until program terminates
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exit_event = m5.simulate(args.abs_max_tick)
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print("Exiting @ tick", m5.curTick(), "because", exit_event.getCause())
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