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arch-arm: Fix IPAS2 invalidation

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Fixing invalidation behaviour for the following stage 2 TLB maintainance
instructions

MISCREG_TLBI_IPAS2E1_Xt
MISCREG_TLBI_IPAS2LE1_X
MISCREG_TLBI_IPAS2E1_Xt
MISCREG_TLBI_IPAS2LE1_Xt

1) Do nothing if EL2 is not enabled in the current security state
2) If we are in secure state, the 63 bit of the Xt register selects
the security domain (s/ns) of the invalidated entries

Change-Id: I4573ed60ce619bcefd9cb05f00c5d3fcfa8d3199
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61751
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2022-07-11 16:59:03 +01:00
parent cc4380b0d6
commit bad3e14bd7
1 changed files with 18 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
src/arch/arm/insts/misc64.cc
View File

@@ -548,13 +548,17 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
case MISCREG_TLBI_IPAS2E1_Xt:
case MISCREG_TLBI_IPAS2LE1_Xt:
{
SCR scr = tc->readMiscReg(MISCREG_SCR);
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIIPA tlbiOp(EL1, secure,
static_cast<Addr>(bits(value, 35, 0)) << 12);
bool secure = release->has(ArmExtension::SECURITY) &&
!scr.ns && !bits(value, 63);
tlbiOp(tc);
TLBIIPA tlbiOp(EL1, secure,
static_cast<Addr>(bits(value, 35, 0)) << 12);
tlbiOp(tc);
}
return;
}
// AArch64 TLB Invalidate by Intermediate Physical Address,
@@ -562,13 +566,17 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
case MISCREG_TLBI_IPAS2E1IS_Xt:
case MISCREG_TLBI_IPAS2LE1IS_Xt:
{
SCR scr = tc->readMiscReg(MISCREG_SCR);
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIIPA tlbiOp(EL1, secure,
static_cast<Addr>(bits(value, 35, 0)) << 12);
bool secure = release->has(ArmExtension::SECURITY) &&
!scr.ns && !bits(value, 63);
tlbiOp.broadcast(tc);
TLBIIPA tlbiOp(EL1, secure,
static_cast<Addr>(bits(value, 35, 0)) << 12);
tlbiOp.broadcast(tc);
}
return;
}
default: