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misc: Use python 3's argumentless super().

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When calling a method in a superclass, you can/should use the super()
method to get a reference to that class. The python 2 version of that
method takes two parameters, the current class name, and the "self"
instance. The python 3 version takes no arguments. This is better for a
at least three reasons.

First, this version is less verbose because you don't have to specify
any arguments.

Second, you don't have to remember which argument goes where (I always
have to look it up), and you can't accidentally use the wrong class
name, or forget to update it if you copy code from a different class.

Third, this version will work correctly if you use a class decorator.
I don't know exactly how the mechanics of this work, but it is referred
to in a comment on this stackoverflow question:

https://stackoverflow.com/questions/681953/how-to-decorate-a-class

Change-Id: I427737c8f767e80da86cd245642e3b057121bc3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52224
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-28 16:16:07 -07:00
parent e4cff7b5ca
commit ba5f68db3d
142 changed files with 301 additions and 370 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/dev/IntPin.py
View File

@@ -33,18 +33,17 @@ Port.compat(INT_SOURCE_ROLE, INT_SINK_ROLE)
# multiple sinks.
class IntSourcePin(VectorPort):
def __init__(self, desc):
super(IntSourcePin, self).__init__(
INT_SOURCE_ROLE, desc, is_source=True)
super().__init__(INT_SOURCE_ROLE, desc, is_source=True)
# Each "physical" pin can be driven by a single source pin since there are no
# provisions for resolving competing signals running to the same pin.
class IntSinkPin(Port):
def __init__(self, desc):
super(IntSinkPin, self).__init__(INT_SINK_ROLE, desc)
super().__init__(INT_SINK_ROLE, desc)
# A vector of sink pins represents a bank of physical pins. For instance, an
# interrupt controller with many numbered input interrupts could represent them
# as a VectorIntSinkPin.
class VectorIntSinkPin(VectorPort):
def __init__(self, desc):
super(VectorIntSinkPin, self).__init__(INT_SINK_ROLE, desc)
super().__init__(INT_SINK_ROLE, desc)

46
src/dev/arm/RealView.py
View File

@@ -604,7 +604,7 @@ class ParentMem(SimpleMemory):
helper via the ParentMem interface.
"""
def __init__(self, *args, **kwargs):
super(ParentMem, self).__init__(*args, **kwargs)
super().__init__(*args, **kwargs)
self._generators = []
def addSubnodeGenerator(self, gen):
@@ -624,7 +624,7 @@ class ParentMem(SimpleMemory):
class MmioSRAM(ParentMem):
def __init__(self, *args, **kwargs):
super(MmioSRAM, self).__init__(**kwargs)
super().__init__(**kwargs)
def generateDeviceTree(self, state):
node = FdtNode("sram@%x" % int(self.range.start))
@@ -913,8 +913,7 @@ class VExpress_EMM(RealView):
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = loc('boot_emm.arm')
super(VExpress_EMM, self).setupBootLoader(
cur_sys, boot_loader, 0x8000000, 0x80000000)
super().setupBootLoader(cur_sys, boot_loader, 0x8000000, 0x80000000)
class VExpress_EMM64(VExpress_EMM):
# Three memory regions are specified totalling 512GiB
@@ -1230,7 +1229,7 @@ Interrupts:
]
def __init__(self, **kwargs):
super(VExpress_GEM5_Base, self).__init__(**kwargs)
super().__init__(**kwargs)
self.clock32KHz.voltage_domain = self.io_voltage
self.clock24MHz.voltage_domain = self.io_voltage
self.system_watchdog.clk_domain = self.dcc.osc_sys
@@ -1273,8 +1272,7 @@ Interrupts:
self.smmu.connect(dev)
def setupBootLoader(self, cur_sys, boot_loader):
super(VExpress_GEM5_Base, self).setupBootLoader(
cur_sys, boot_loader, 0x8000000, 0x80000000)
super().setupBootLoader(cur_sys, boot_loader, 0x8000000, 0x80000000)
# Setup m5ops. It's technically not a part of the boot
# loader, but this is the only place we can configure the
@@ -1302,7 +1300,7 @@ Interrupts:
def generateDeviceTree(self, state):
# Generate using standard RealView function
dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state))
dt = list(super().generateDeviceTree(state))
if len(dt) > 1:
raise Exception("System returned too many DT nodes")
node = dt[0]
@@ -1344,11 +1342,10 @@ class VExpress_GEM5_V1_Base(VExpress_GEM5_Base):
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = [ loc('boot.arm64'), loc('boot.arm') ]
super(VExpress_GEM5_V1_Base, self).setupBootLoader(
cur_sys, boot_loader)
super().setupBootLoader(cur_sys, boot_loader)
def _on_chip_devices(self):
return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [
return super()._on_chip_devices() + [
self.gic, self.vgic, self.gicv2m,
]
@@ -1364,9 +1361,7 @@ class VExpress_GEM5_V1_HDLcd(VExpress_GEM5_V1_Base):
pio_addr=0x2b000000, interrupt=ArmSPI(num=95))
def _on_chip_devices(self):
return super(VExpress_GEM5_V1_HDLcd,self)._on_chip_devices() + [
self.hdlcd,
]
return super()._on_chip_devices() + [self.hdlcd,]
class VExpress_GEM5_V2_Base(VExpress_GEM5_Base):
gic = Gicv3(dist_addr=0x2c000000, redist_addr=0x2c010000,
@@ -1377,15 +1372,12 @@ class VExpress_GEM5_V2_Base(VExpress_GEM5_Base):
gic.cpu_max = 128
def _on_chip_devices(self):
return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [
self.gic, self.gic.its
]
return super()._on_chip_devices() + [self.gic, self.gic.its]
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = [ loc('boot_v2.arm64') ]
super(VExpress_GEM5_V2_Base, self).setupBootLoader(
cur_sys, boot_loader)
super().setupBootLoader(cur_sys, boot_loader)
class VExpress_GEM5_V2(VExpress_GEM5_V2_Base):
"""
@@ -1399,9 +1391,7 @@ class VExpress_GEM5_V2_HDLcd(VExpress_GEM5_V2_Base):
pio_addr=0x2b000000, interrupt=ArmSPI(num=95))
def _on_chip_devices(self):
return super(VExpress_GEM5_V2_HDLcd,self)._on_chip_devices() + [
self.hdlcd,
]
return super()._on_chip_devices() + [self.hdlcd,]
class VExpress_GEM5_Foundation(VExpress_GEM5_Base):
"""
@@ -1439,18 +1429,12 @@ class VExpress_GEM5_Foundation(VExpress_GEM5_Base):
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
def _on_chip_devices(self):
return super(VExpress_GEM5_Foundation, self)._on_chip_devices() + [
self.gic
]
return super()._on_chip_devices() + [self.gic]
def _off_chip_devices(self):
return super(VExpress_GEM5_Foundation, self)._off_chip_devices() + [
self.clcd,
self.sp810_fake,
]
return super()._off_chip_devices() + [self.clcd, self.sp810_fake,]
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = [ loc('boot_v2.arm64') ]
super(VExpress_GEM5_Foundation, self).setupBootLoader(
cur_sys, boot_loader)
super().setupBootLoader(cur_sys, boot_loader)

3
src/dev/arm/VExpressFastmodel.py
View File

@@ -57,5 +57,4 @@ class VExpressFastmodel(VExpress_GEM5_Base):
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = [ loc('boot_v2.arm64') ]
super(VExpressFastmodel, self).setupBootLoader(
cur_sys, boot_loader)
super().setupBootLoader(cur_sys, boot_loader)

2
src/dev/arm/css/Scmi.py
View File

@@ -57,7 +57,7 @@ class ScmiChannel(SimObject):
"This is the doorbell used to notify the SCMI platform")
def __init__(self, shmem, *args, **kwargs):
super(ScmiChannel, self).__init__(**kwargs)
super().__init__(**kwargs)
def shmemGenerator(state):
shmem_node = FdtNode("scp-shmem@%x" % 0)

4
src/dev/net/Ethernet.py
View File

@@ -47,11 +47,11 @@ Port.compat(ETHERNET_ROLE, ETHERNET_ROLE)
class EtherInt(Port):
def __init__(self, desc):
super(EtherInt, self).__init__(ETHERNET_ROLE, desc)
super().__init__(ETHERNET_ROLE, desc)
class VectorEtherInt(VectorPort):
def __init__(self, desc):
super(VectorEtherInt, self).__init__(ETHERNET_ROLE, desc)
super().__init__(ETHERNET_ROLE, desc)
class EtherLink(SimObject):
type = 'EtherLink'