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misc: Fix coding style for union's opening braces

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The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *union [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>union X ... {

by:

    <indent level>union X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^union ([A-Za-z].*) \{$/union \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    union ([A-Za-z].*) \{$/    union \1\n    \{/g'

and so on.

Change-Id: I066854eb27a8acd2cc2dfa41596bb1b1f66c71b1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43328
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Daniel R. Carvalho
2021-03-19 19:11:44 -03:00
committed by Daniel Carvalho
parent df8ef51d61
commit b2c0b191e1
7 changed files with 38 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/dev/pci/pcireg.h
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@@ -64,7 +64,8 @@ BitUnion16(PciCommandRegister)
Bitfield<0> ioSpace;
EndBitUnion(PciCommandRegister)
union PCIConfig {
union PCIConfig
{
uint8_t data[64];
struct {
@@ -216,7 +217,8 @@ union PCIConfig {
* Defines the Power Management capability register and all its associated
* bitfields for a PCIe device.
*/
union PMCAP {
union PMCAP
{
uint8_t data[6];
struct {
uint16_t pid; /* 0:7 cid
@@ -249,7 +251,8 @@ union PMCAP {
* can be filled in if a device model supports both, but only 1 of
* MSI/MSIX/INTx interrupt mode can be selected at a given time.
*/
union MSICAP {
union MSICAP
{
uint8_t data[24];
struct {
uint16_t mid; /* 0:7 cid
@@ -276,7 +279,8 @@ union MSICAP {
* Defines the MSI-X Capability register and its associated bitfields for
* a PCIe device.
*/
union MSIXCAP {
union MSIXCAP
{
uint8_t data[12];
struct {
uint16_t mxid; /* 0:7 cid
@@ -296,7 +300,8 @@ union MSIXCAP {
};
};
union MSIXTable {
union MSIXTable
{
struct {
uint32_t addr_lo;
uint32_t addr_hi;