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FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking.

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Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.

arch/alpha/alpha_memory.cc:
    The regfile has been changed so it no longer has the opcode and ra.  Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
    Moved code that once existed within simpleCPU to ev5, and templatized it.
    This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
    Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
    Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
    Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
    Removed opcode and ra from the regfile.  The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
    Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
    Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
    Added in a more generic trap function so "ev5_trap" doesn't need to be called.  It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
    Exec context now has the instruction within it.  Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
    Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
    Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
    Added declaration for execute() using FastCPUExecContext.

--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
This commit is contained in:
Kevin Lim
2004-05-27 17:46:16 -04:00
parent 2cc4fd87eb
commit a896960cbf
10 changed files with 167 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/alpha/alpha_memory.cc
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@@ -425,8 +425,8 @@ AlphaDTB::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
ipr[AlphaISA::IPR_VA] = vaddr;
// set MM_STAT register flags
ipr[AlphaISA::IPR_MM_STAT] = (((xc->regs.opcode & 0x3f) << 11)
| ((xc->regs.ra & 0x1f) << 6)
ipr[AlphaISA::IPR_MM_STAT] = (((OPCODE(xc->getInst()) & 0x3f) << 11)
| ((RA(xc->getInst()) & 0x1f) << 6)
| (flags & 0x3f));
// set VA_FORM register with faulting formatted address

67
arch/alpha/ev5.cc
View File

@@ -6,6 +6,7 @@
#include "sim/debug.hh"
#endif
#include "cpu/exec_context.hh"
#include "cpu/fast_cpu/fast_cpu.hh"
#include "sim/sim_events.hh"
#include "targetarch/isa_traits.hh"
#include "base/remote_gdb.hh"
@@ -100,6 +101,64 @@ AlphaISA::initIPRs(RegFile *regs)
}
template <class XC>
void
AlphaISA::processInterrupts(XC *xc)
{
//Check if there are any outstanding interrupts
//Handle the interrupts
int ipl = 0;
int summary = 0;
IntReg *ipr = xc->getIprPtr();
check_interrupts = 0;
if (ipr[IPR_ASTRR])
panic("asynchronous traps not implemented\n");
if (ipr[IPR_SIRR]) {
for (int i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
if (ipr[IPR_SIRR] & (ULL(1) << i)) {
// See table 4-19 of the 21164 hardware reference
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
summary |= (ULL(1) << i);
}
}
}
uint64_t interrupts = xc->intr_status();
if (interrupts) {
for (int i = INTLEVEL_EXTERNAL_MIN;
i < INTLEVEL_EXTERNAL_MAX; i++) {
if (interrupts & (ULL(1) << i)) {
// See table 4-19 of the 21164 hardware reference
ipl = i;
summary |= (ULL(1) << i);
}
}
}
if (ipl && ipl > ipr[IPR_IPLR]) {
ipr[IPR_ISR] = summary;
ipr[IPR_INTID] = ipl;
xc->trap(Interrupt_Fault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
ipr[IPR_IPLR], ipl, summary);
}
}
template <class XC>
void
AlphaISA::zeroRegisters(XC *xc)
{
// Insure ISA semantics
xc->setIntReg(ZeroReg, 0);
xc->setFloatRegDouble(ZeroReg, 0.0);
}
void
ExecContext::ev5_trap(Fault fault)
{
@@ -585,4 +644,12 @@ ExecContext::simPalCheck(int palFunc)
return true;
}
//Forward instantiation for FastCPU object
template
void AlphaISA::processInterrupts(FastCPU *xc);
//Forward instantiation for FastCPU object
template
void AlphaISA::zeroRegisters(FastCPU *xc);
#endif // FULL_SYSTEM

2
arch/alpha/ev5.hh
View File

@@ -71,6 +71,8 @@
#define MM_STAT_ACV_MASK 0x0002
#define MM_STAT_WR_MASK 0x0001
#define OPCODE(X) (X >> 26) & 0x3f
#define RA(X) (X >> 21) & 0x1f
////////////////////////////////////////////////////////////////////////
//

37
arch/alpha/isa_desc
View File

@@ -22,6 +22,7 @@ let {{
#include "base/misc.hh"
#include "cpu/exec_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/fast_cpu/fast_cpu.hh"
#include "cpu/full_cpu/dyn_inst.hh"
#include "cpu/simple_cpu/simple_cpu.hh"
#include "cpu/static_inst.hh"
@@ -312,6 +313,9 @@ declare {{
Fault execute(SimpleCPUExecContext *, Trace::InstRecord *)
{ return No_Fault; }
Fault execute(FastCPUExecContext *, Trace::InstRecord *)
{ return No_Fault; }
Fault execute(FullCPUExecContext *, Trace::InstRecord *)
{ return No_Fault; }
};
@@ -719,6 +723,9 @@ declare {{
Fault execute(SimpleCPUExecContext *, Trace::InstRecord *)
{ panic("attempt to execute eacomp"); }
Fault execute(FastCPUExecContext *, Trace::InstRecord *)
{ panic("attempt to execute eacomp"); }
Fault execute(FullCPUExecContext *, Trace::InstRecord *)
{ panic("attempt to execute eacomp"); }
};
@@ -739,6 +746,9 @@ declare {{
Fault execute(SimpleCPUExecContext *, Trace::InstRecord *)
{ panic("attempt to execute memacc"); }
Fault execute(FastCPUExecContext *, Trace::InstRecord *)
{ panic("attempt to execute memacc"); }
Fault execute(FullCPUExecContext *, Trace::InstRecord *)
{ panic("attempt to execute memacc"); }
};
@@ -1452,6 +1462,14 @@ declare {{
return Unimplemented_Opcode_Fault;
}
Fault execute(FastCPUExecContext *xc,
Trace::InstRecord *traceData)
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
return Unimplemented_Opcode_Fault;
}
Fault execute(FullCPUExecContext *xc,
Trace::InstRecord *traceData)
{
@@ -1502,6 +1520,17 @@ declare {{
return No_Fault;
}
Fault execute(FastCPUExecContext *xc,
Trace::InstRecord *traceData)
{
if (!warned) {
warn("instruction '%s' unimplemented\n", mnemonic);
warned = true;
}
return No_Fault;
}
Fault execute(FullCPUExecContext *xc,
Trace::InstRecord *traceData)
{
@@ -1573,6 +1602,14 @@ declare {{
return Unimplemented_Opcode_Fault;
}
Fault execute(FastCPUExecContext *xc,
Trace::InstRecord *traceData)
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
return Unimplemented_Opcode_Fault;
}
Fault execute(FullCPUExecContext *xc,
Trace::InstRecord *traceData)
{

10
arch/alpha/isa_traits.hh
View File

@@ -33,6 +33,7 @@
#include "targetarch/faults.hh"
#include "base/misc.hh"
class FastCPU;
class FullCPU;
class Checkpoint;
@@ -156,8 +157,6 @@ class AlphaISA
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
#endif // FULL_SYSTEM
// Are these architectural, or just for convenience?
uint8_t opcode, ra; // current instruction details (for intr's)
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
@@ -233,6 +232,13 @@ class AlphaISA
ConfigNode *node,
RegFile &regs);
#endif
/**
* Function to insure ISA semantics about 0 registers.
* @param xc The execution context.
*/
template <class XC>
static void zeroRegisters(XC *xc);
};

4
arch/isa_parser.py
View File

@@ -1387,6 +1387,7 @@ class InstObjParams:
self.base_class = base_class
self.exec_func_declarations = '''
Fault execute(SimpleCPUExecContext *, Trace::InstRecord *);
Fault execute(FastCPUExecContext *, Trace::InstRecord *);
Fault execute(FullCPUExecContext *, Trace::InstRecord *);
'''
if code_block:
@@ -1433,7 +1434,8 @@ class InstObjParams:
error(0, 'InstObjParams::subst: undefined template "%s"' % t)
if template.find('%(cpu_model)') != -1:
tmp = ''
for cpu_model in ('SimpleCPUExecContext', 'FullCPUExecContext'):
for cpu_model in ('SimpleCPUExecContext', 'FastCPUExecContext',
'FullCPUExecContext'):
self.cpu_model = cpu_model
tmp += self._subst(template)
result.append(tmp)

15
cpu/exec_context.cc
View File

@@ -106,6 +106,7 @@ ExecContext::serialize(ostream &os)
regs.serialize(os);
// thread_num and cpu_id are deterministic from the config
SERIALIZE_SCALAR(func_exe_inst);
SERIALIZE_SCALAR(inst);
#ifdef FULL_SYSTEM
bool ctx = false;
@@ -143,6 +144,7 @@ ExecContext::unserialize(Checkpoint *cp, const std::string &section)
regs.unserialize(cp, section);
// thread_num and cpu_id are deterministic from the config
UNSERIALIZE_SCALAR(func_exe_inst);
UNSERIALIZE_SCALAR(inst);
#ifdef FULL_SYSTEM
bool ctx;
@@ -233,3 +235,16 @@ ExecContext::regStats(const string &name)
kernelStats.regStats(name + ".kern");
#endif
}
void
ExecContext::trap(Fault fault)
{
//TheISA::trap(fault); //One possible way to do it...
/** @todo: Going to hack it for now. Do a true fixup later. */
#ifdef FULL_SYSTEM
ev5_trap(fault);
#else
fatal("fault (%d) detected @ PC 0x%08p", fault, readPC());
#endif
}

24
cpu/exec_context.hh
View File

@@ -31,6 +31,7 @@
#include "sim/host.hh"
#include "mem/mem_req.hh"
#include "mem/functional_mem/functional_memory.hh"
#include "sim/serialize.hh"
// forward declaration: see functional_memory.hh
@@ -114,6 +115,9 @@ class ExecContext
// pointer to CPU associated with this context
BaseCPU *cpu;
// Current instruction
MachInst inst;
// Index of hardware thread context on the CPU that this represents.
int thread_num;
@@ -311,6 +315,18 @@ class ExecContext
virtual bool misspeculating();
MachInst getInst() { return inst; }
void setInst(MachInst new_inst)
{
inst = new_inst;
}
Fault instRead(MemReqPtr &req)
{
return mem->read(req, inst);
}
//
// New accessors for new decoder.
//
@@ -395,6 +411,14 @@ class ExecContext
bool simPalCheck(int palFunc);
#endif
/** Meant to be more generic trap function to be
* called when an instruction faults.
* @param fault The fault generated by executing the instruction.
* @todo How to do this properly so it's dependent upon ISA only?
*/
void trap(Fault fault);
#ifndef FULL_SYSTEM
IntReg getSyscallArg(int i)
{

3
cpu/simple_cpu/simple_cpu.cc
View File

@@ -708,8 +708,7 @@ SimpleCPU::tick()
xc->regs.pc);
#ifdef FULL_SYSTEM
xc->regs.opcode = (inst >> 26) & 0x3f;
xc->regs.ra = (inst >> 21) & 0x1f;
xc->setInst(inst);
#endif // FULL_SYSTEM
xc->func_exe_inst++;

8
cpu/static_inst.hh
View File

@@ -43,6 +43,8 @@
class ExecContext;
class DynInst;
typedef DynInst FullCPUExecContext;
class FastCPU;
typedef FastCPU FastCPUExecContext;
class SimpleCPU;
typedef SimpleCPU SimpleCPUExecContext;
class SymbolTable;
@@ -310,6 +312,12 @@ class StaticInst : public StaticInstBase
virtual Fault execute(SimpleCPUExecContext *xc,
Trace::InstRecord *traceData) = 0;
/**
* Execute this instruction under FastCPU model.
*/
virtual Fault execute(FastCPUExecContext *xc,
Trace::InstRecord *traceData) = 0;
/**
* Execute this instruction under detailed FullCPU model.
*/